6 Replies Latest reply on Mar 21, 2014 9:25 AM by WeGa_288606

    Power Notation in PSOC data sheets




      I am on a tangent to improve my understanding of the PSOC power pins, notation, and uses. I have bee studying AN61290 "PSoC 3 and PSoC 5LP" Hardware Design Considerations" as well as some reference designs provided with the various development kits and data sheets. 




      Clarity and/or confirmation on items in yellow/red highlight would be highly appreciated:




      VDDA and VCCA are analog supply pins. What is the difference between the two?


      VDDD and VCCD are digital supply pins What is the difference between the two?


      VSSA analog ground pins??


      VSSD digital ground pins??




      VDDIO0,  VDDIO1,  VDDIO2,  VDDIO3 digital supply pins supporting various supply domains i.e. 1.8V, 3.3V. 5V must be less than or equal to VSSA




      In document NO CY8C58LP_0010-84932_0E




      1. All VDDIOx pins are supplied by VDDD. I think I am fine with this assuming all I/O are in the same digital domain but if they were on different domains then each domain would benefit from its own respective ground at least upto the tie in point no? 




      2. VSSD is shown having a separate supply source on PIN 66  but then tied to ground on PIN 87 (Page 8 TQFP) is this simply a decoupling here??




      3. Is the idea that VSSD pins are scattered throughout the PSoC to provide routing and place options?




      4. Intended difference between VSSD and VDDD in this particular reference i.e. VDDD is shown from one source while VSSD is shown from another ?? Why? For some reason I am under the impression that VSSD is digital ground but here it is shown to have a source connection....so clearly I am confused here :) 


      In drawing CY8CKIT-014 PSoC 5 FirstTouch Starter Kit 

      1. All VSSD pins are tied to ground??? Is this just because it is a starter kit thus cost was an issue and no attempt to separate analog/digital supply was needed in this design?


      Sorry if this is long winded but I really want to sort through all these power pins on the PSoC. Its a maze for me! I am not really a power guru as you can probably tell. 









        • 1. Re: Power Notation in PSOC data sheets

          I would have to check on this but I believe all Vss pins are tied into the substrate,


          and the fact that there are several of them is to insure there is no voltage gradient


          across the substrate which would lead to a source bulk effect on thresholds in the


          regions where devices most remote from "true" ground.




          Regards, Dana.

          • 2. Re: Power Notation in PSOC data sheets

            Regarding grounding, there is great article by Analog Devices: Staying well grounded. Basic recommendation: analog and digital grounds are connected together directly at the chip. If its doing precision analog, this ground then goes to global analog ground (if there is any).


            There are multiple Vssd pins to have low impedance connections inside of the chip. So all of them must be connected together - they are not there to ease your routing.


            Vcc and Vdd pins are not the same! Vdd pins are power inputs. But the Vcc pins are the outputs of the internal voltage regulators, and must be decoupled to ground externally (read the PSoC5 data sheet for your device, its explains the different pins).

            • 3. Re: Power Notation in PSOC data sheets

              A whole other related topic is the caps used on supply to bypass.




              Look carefully at datasheets of caps, the same WVDC and C from one cap


              to another can show great differences in AC performance. Not to ignore wildy


              changing C with V some caps exhibit. A lot of ewffort by some C vendors has


              gone into package lead L reduction to improve ESR performance.




              Polymer caps best in class for bulk Tantalum use. They have an order of magnitude


              better ESR performance than regular tants.




              Also some regulators want a specific range of cap on output, thereby prohibiting


              you from using ultra low ESR types of caps. Of course you can always "de-couple"


              the regulator from low ESR C thru use of L or R (ech).




              Multilayer ceramics to get at the high freq stuff.




              Regards, Dana.

              • 4. Re: Power Notation in PSOC data sheets

                 Thanks for the replies and suggestions everyone. I still have many questions that need sorting. Perhaps we can tackle them one by one. Take for example document NO CY8C58LP_001-84932_0E




                1. Page 10: defines VSSD: as ground for all digital logic and I/O pins.


                2. Page 8: Shows VSSD tied to a source on PIN 66 but also shows it tied to a ground on PIN 38


                How is the VSSD source on PIN 66 different than the main VDDD lines?


                What is the purpose of tieing VSSD to a seperate supply on PIN 66 and then grounding it on PIN 38?

                VSSD from what I can tell is not discussed or documented as a source pin but rather a digital ground in both data sheet and application note referenced in my first post.




                • 5. Re: Power Notation in PSOC data sheets

                  I cannot find your mentioned document, can you please post a link to it?





                  • 6. Re: Power Notation in PSOC data sheets

                    I guess the document you are referring to is the "PSoC5LP CY8c58 family data sheet" (sorry, my crystal ball is still in repair :)


                    These pins are not different. All Vss* pins need to be connected to ground. That the ground connection for Pin 38 and for pin 66 use different symbols is a mistake of the schematic designer - but the nets are clearly labelled as 'VSSD' for both. Vssd is not a source pin but ground, and its defined as such.