"(Digital, Analog and IO pins are tied together)"
What do you mean by this ?
Are you doing this in a DVK board ? If so which one.
Nope, it's on a custom circuit board.
Tied together means, in this case, that they all share the same voltage source. On the board, the pins VDDD, VDDA and VDDIOx are all connected to a single terminal.
Yep, seen it already, although I haven't actually applied any of the recommendations since I'm just trying to measure the static consumption.
Actually, I'm just trying to assess the best method to measure power consumption. I therefore need to know a configuration whose consumption is known (e.g. ~2µA in Sleep).
The only problem is that when I get to Hibernate, the measurements are not following the trend.
I haven't been working with the device lately (been working on something else),
But today I have finally solved the problem.
In the DWR file, I changed the Programming/Debugging mode to GPIO and for the sake of it, I enabled Device Protection. I don't think it's necessary, but what the heck.
And voila, it worked neatly. I got a baseline consumption of about 140 nA (kinda worrying if you ask me, it should be a bit higher).
I'm not sure why it didn't work before, but my guess is that since I had the Programming/Debugging option set to SWD/SWV beforehand, the PSoC might be trying to stream debug data thru the debug port and maybe that consumes current (not sure how, since the MiniProg is disconnected) or it woke the PSoC up (again, the pins are not connected to each other, so how is that even possible).
Oh, I also changed the Temp Range to 0 - 85/125 C. Could it be possible that that parameter causes the consumption to drop as well?
As you can see the temp range defines the limits within the announced power consumption will be fulfilled. Since you are not working at 85°C (presumably) your device consumes less than the specified rating.
I'm at the same issue today (low energy) and I read the AN Dana linked, and on page 12 there is a chapter "Is Your Debug Interface Running? " where this is described. This could help you to understand what happened (although you described it).
Power consumption in CMOS a tad complicated. As T rises Rdson rises,
dues to Vth rising, so switched R load based Pdiss drops. But then leakage
rises dramatically with T, increasing that componet of Pdiss.
Switching based Pdiss laregly just a f( f,C, V ).
If you look at datasheet you will see Idd largely flat over T -