Yes, of course this is possible for PSoC1/3 and 5, only PSoC4 is restricted with clock distribution. For max. frequencies have a look into the PWM datasheet.
I would suggest you to download and run Creator 3, there you can start a new project, connect an input pin to a PWM and compile.
Even though this is PSOC 4 there is a reference to using the approach with PSOC 3, 5LP. I
thinks its a not so subtle hint that meeting timing in any of the 3/4/5LP families should be
done this way.
Thanks for your help. I was hoping it was possible to clock the UDB peripherals at a rate higher than the internal core clock. It looks like that's not the case and, at least for the PWM case, are limited to 68MHz max.