your Verilog is clean, but the functionality of the state machine is too large to fitt into PSoC4 42xx.
a. use PSoC5LP or wait some time for new PSoC4 devices with more UDB's
b. reduce functionality
Well that upsets me a lot..
Do you know what is taking up the "pterms" I could try and trim it down if i knew where to look.., I have to use this chip its all been built. I never thought such a small state machine would take over the 4 full UDB's
search cypress.com with Verilog keyword. Thera are nice Application notes and Verilog demos. Think, UDB is not the same as pterms where warp fits the code ....
PTerms are programmable logic that can be compared to the formerly used "PALs", look here: en.wikipedia.org/wiki/Programmable_Array_Logic
Within an UDB is a number of such programmable logic lines which are used to build the logic to generate the compares to decide which state you are in and which state will be next.
Since the count of these logic lines is restricted you can easily run out of this resource, particularly when using a PSoC4 which has got only 4 UDBs compared to 24 of a PSoC5.
A chance to reduce the number of used pterms could be done by
Replacing components that are UDB-based with fixed-function components
Reducing used gates in the schematic
Reducing the number of states of your state-machine
I just ran a test: It looks like when using an LUT-component that does not increase the number of used Pterms, so you could put part of your state-machine into an LUT. At least it is worth a try.
Oops, not paying attention, no DFB in PSOC 4. Ignore my post.
I would guess its due to having too much state. Each bit of state that needs to be stored blocks one macro cell (utilizing the DFF in there). So try to reduce that. (and even if the DFFs itself are fine, since they are spread over multiple macrocells, connecting them needs PTERMs)
I recommend examining the "macrocell listing" portion of your rpt file to determine what's taking up all your pterms. I scanned through it quickly and it seems that many of the pterms are being consumed by your password functionality. For example, this equation (generated from the synthesis of your verilog) uses 8 pterms:
MacroCell: Name=\AlarmSystem:MODULE_1:g1:a0:xeq_split\, Mode=(Combinatorial)
Total # of inputs : 10
Total # of product terms : 8
Clock Enable: True
Main Equation : 8 pterms
\AlarmSystem:currentPassword_4\ * !Net_260_4
+ \AlarmSystem:currentPassword_3\ * !Net_260_3
+ !\AlarmSystem:currentPassword_2\ * Net_260_2
+ \AlarmSystem:currentPassword_2\ * !Net_260_2
+ !\AlarmSystem:currentPassword_1\ * Net_260_1
+ \AlarmSystem:currentPassword_1\ * !Net_260_1
+ !\AlarmSystem:currentPassword_0\ * Net_260_0
+ \AlarmSystem:currentPassword_0\ * !Net_260_0
Output = \AlarmSystem:MODULE_1:g1:a0:xeq_split\ (fanout=1)
The product terms are the inputs to the equation (combined by logical OR '+'). I see a few other big product term equations also involving your password functionality. I also see in your verilog where you are making several equality compares involving the password. Try reducing the password length by a bit or two, and I'll bet you'll be able to fit.
It might be possible to implement your password function in the datapath block, potentially saving a bunch of pterms and some macrocells. Equality and greater than / less than comparisons are things that the datapath block does well. A UDB editor was added to PSoC Creator in v3.0 to make datapath development easier. Go to this link and scroll down to find "Using the UDB Editor" to watch a 6-part tutorial video: http://www.cypress.com/?rID=40547
Thanks guys that's such a big help. To be honest this project is for University and was meant to be built on an Altera board, the code has to be constructed that way as its been specified to be fully verilog.
I wanted to try and use the PSoCs instead of the altera silicon but I just didn't anticipate how little digital fabric the PSoC 4 has..
I think I am going to have to complete it on the Altera board and just remember I will have to use LUTs and Datapaths the next time i want to use this chip..