When you use Vssa to Vdd the internal Vref 1.024 V is not being used, the conversion
is ratiometric to the Vdd supply.
Thanks for the answer,
I don't understand in which sense the reference is ratiometric?you mean that the input between 0-5 V is automatically ratioed to 4 in the way to have a signal between 0 and 1.25 V at the input of ADC? I question this because When i set vssa to vdd the reference showed in the component is 1.25V that is VDD/4 in my case.
Thanks for the answer . If i understood correctly from the document , once the input signal between vssa and vdd goes to the ADC , it is reduced by a resistior divider in order to fall in the dynamic 0-1.25V and in this way it is possible to use the 1.25 as voltage reference?
Ratiometric in this case means that the input is referenced to the supply voltage. That is especially useful when the input signal is derived from the supply - e.g. by a voltage divider. Then changes to the supply voltage affect both the input voltage and the reference voltage, by the same amount. This increases accurany despite the supply voltage not being all that accurate.
If tthis is not what you want, attenuate the input signal using a resistor divider and then use the internal reference (don't forget to use a bypass cap).
If you are looking for absolute accuracy then use Vref of 1.024 internal, as ratiometric
is anything but single measurement absolute accurate, as its ref is a f(Vdd). Unless
you supply the Vdd of PSOC with a precision reference.
In your case I recomend you use Vref of 1.024 and Vssa to 6.144 V (Vssa to 6*Vref)
for in put range to get absolute accurate Vssa - 100 mV to Vdda + 100 mV measure-
the final thing that i would like to know and i don't understand is that how it is possible to use an ADC reference of 1.024V and a signal that goes from vssa to about 6V? I mean for example If I have a signal of 4V , how the ADC will convert this value whether the maximum value it reads is the reference 1.024V?
I believe it is done by controling charge transfer thru ratioed capacitors in the modulator,
but will confirm this by filing a CASE at Cypress.
Here is the results from tech support -
Yes, we have confirmation that the higher input range is achieved by reducing the modulator gain
through through reduction of the capacitor ratio.
Page 385 of the below linked PSoC3 Technical Reference Manual describes about this gain
configuration in the Delta Sigma modulator:
<a href="http://www.cypress.com/?docID=46233"> PSoC3 Technical Reference Manual </a>