Your ADC is configured into differential mode, is this what you want? In that mode, there are some limitation regarding commong mode voltage. Also, did you read the component data sheet with regards to the limitations of the input voltages?
This might help -
http://www.cypress.com/?rID=39677 AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
http://www.cypress.com/?rID=43337 AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations
http://www.cypress.com/?rID=40247 AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations
As hli points out look at graphic of CM range in config tool. If you bypass the buffer you will get/exceed true R-R performance.
Yes I'm measuring the differential voltage across two pins and I am utilizing pins that, according to the documentation, have higher accuracy for analog purposes.
The datasheet doesn't discuss any limitations on input voltage on the low end, only on the high end.
With regards to the common mode voltage, unless I'm misunderstanding something, I am getting nowhere near exceeding the input range (+/- 64000mV when I'm only reading in, at most, around 15 mV).
Sorry, 64000 uV, not mV
If you read the ap notes bypassing Vref importent as well.
Attached some old but very applicable ap notes on signal path
errors and dealing with them.
Is this your own layout or you using a Cypress DVK ?
All AtoD Error11.zip 12.1 MB
Another area of concern is bulk cap performance, Polymer Tanatalum
best, an order of magnitude better z(f) performance than traditional
Multilayer ceramic as well for higher f noise suppression.