2 Replies Latest reply on Oct 10, 2017 12:59 AM by KandlaguntaR_36

    FX3: Why does 32-bit Slave Fifo conflict with SPI?

    jonathan.szymaniak
    jonathan.szymaniak Aug 18, 2017 3:39 PM

      Hi there,

      The CYUSB301x manual (001-52136 Rev. *N), states: "When GPIF II is configured for the 32-bit data bus width, GPIO[50]-GPIO[52] may be configured as GPIOs or I2S, and GPIO[53] to GPIO[56] may be configured as
      GPIOs or UART interface only."

      Could someone elaborate on exactly why the SPI peripheral becomes unavailable when using a 32-bit GPIF II bus?  I see no physical pin conflicts; GPIO[53] - GPIO [56] certainly don't overlap the GPIF II data or control signals, as far as I can tell.

      I assume there must be some internal signal muxing/routing conflict, or other internal resource contention? If so, could someone share some details on this? 

      Thank you,

      Jon

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        • 1. Re: FX3: Why does 32-bit Slave Fifo conflict with SPI?
          burtond_1573671
          burtond_1573671 Feb 16, 2016 8:17 AM (in response to jonathan.szymaniak)

          I would like to know the answer to that as well.  I did see elsewhere in the forum that you can implement SPI in software using GPIO. I would like to know why the SPI function and 32-bit FIFO conflict.

             

           

             

          Doug

          • 2. Re: FX3: Why does 32-bit Slave Fifo conflict with SPI?
            KandlaguntaR_36
            KandlaguntaR_36 Moderator Oct 10, 2017 12:59 AM (in response to burtond_1573671)

            SPI can be used for Booting purpose, even you configure the GPIF II with 32-bit in the firmware.

             

            Booting process explained here

             

            When ROM Bootloader samples the PMODE lines (0Z1) and it comes to know that it has to boot from the SPI Flash.

            Therefore, it boots the Firmware to System RAM.

            Once the firmware image has been completely transferred, the FX3 bootloader automatically jumps to the

            entry point of the newly downloaded firmware and starts executing.

             

            Then, all the blocks will be configured as per the FIRMWARE Loaded from SPI.

            Once it is configured, GPIF II with 32-bit data bus, SPI Block will not be available for any SPI Communication.