1 Reply Latest reply on Feb 16, 2016 8:17 AM by burtond_1573671

    FX3: Why does 32-bit Slave Fifo conflict with SPI?

    jonathan.szymaniak

      Hi there,

      The CYUSB301x manual (001-52136 Rev. *N), states: "When GPIF II is configured for the 32-bit data bus width, GPIO[50]-GPIO[52] may be configured as GPIOs or I2S, and GPIO[53] to GPIO[56] may be configured as
      GPIOs or UART interface only."

      Could someone elaborate on exactly why the SPI peripheral becomes unavailable when using a 32-bit GPIF II bus?  I see no physical pin conflicts; GPIO[53] - GPIO [56] certainly don't overlap the GPIF II data or control signals, as far as I can tell.

      I assume there must be some internal signal muxing/routing conflict, or other internal resource contention? If so, could someone share some details on this? 

      Thank you,

      Jon