11 Replies Latest reply on May 2, 2014 5:44 AM by user_14586677

    verilog base FIR filter madule

    soha.gh

      hi 

         

      I want to implement a FFT transform verilog based module with psoc5lp

         

      my verilog code is true and its fine in quartus software but when i use it in psoc creator it has some error

         

      i think that the psoc creator can't get all of the verilog command as well as simple command

         

      please help me

         

      thanks

        • 1. Re: verilog base FIR filter madule
          soha.gh

          I want to implement a FIR filter verilog based module with psoc5lp

             

          my verilog code is true and its fine in quartus software but when i use it in psoc creator it has some error

             

          i think that the psoc creator can't get all of the verilog command as well as simple command

             

          please help me

             

          thanks

          • 2. Re: verilog base FIR filter madule
            user_44074550

             Hi soha, 

               

            please attach your Verilog code .....

               

            Regards, 

               

            Viktor

            • 3. Re: verilog base FIR filter madule
              user_78878863

              Also, when asking about an error, it helps to state what the error actually is. My crystal ball is still out of order, unfortunately :(

              • 4. Re: verilog base FIR filter madule
                soha.gh

                my verilog code and complete project is here:

                   

                 

                   

                module FIR_v1_00 (
                input clock,
                  input reset,
                  input wire[15:0] input_sample,
                  output reg[15:0] output_sample);

                parameter N = 13;
                reg signed[15:0] coeffs[12:0];
                reg [15:0] holderBefore[12:0];
                wire [15:0] toAdd[12:0];

                always @(*)
                begin
                    coeffs[0]=6375;
                    coeffs[1]=1;
                    coeffs[2]=-3656;
                    coeffs[3]=3;
                    coeffs[4]=4171;
                    coeffs[5]=4;
                    coeffs[6]=28404;
                    coeffs[7]=4;
                    coeffs[8]=4171;
                    coeffs[9]=3;
                    coeffs[10]=-3656;
                    coeffs[11]=1;
                    coeffs[12]=6375;
                end

                genvar i;

                generate
                for (i=0; i<N; i=i+1)
                    begin: mult
                        multiplier mult1(
                          .dataa(coeffs[i]),
                          .datab(holderBefore[i]),
                          .result(toAdd[i]));
                    end
                endgenerate

                always @(posedge clock or posedge reset)
                begin
                    if(reset)
                        begin
                            holderBefore[12]    <= 0;
                            holderBefore[11]    <= 0;
                            holderBefore[10]    <= 0;
                            holderBefore[9]     <= 0;
                            holderBefore[8]     <= 0;
                            holderBefore[7]     <= 0;
                            holderBefore[6]     <= 0;
                            holderBefore[5]     <= 0;
                            holderBefore[4]     <= 0;
                            holderBefore[3]     <= 0;
                            holderBefore[2]     <= 0;
                            holderBefore[1]     <= 0;
                            holderBefore[0]     <= 0;
                            output_sample       <= 0;
                        end
                    else
                        begin              
                            holderBefore[12]    <= holderBefore[11];
                            holderBefore[11]    <= holderBefore[10];
                            holderBefore[10]    <= holderBefore[9];
                            holderBefore[9]     <= holderBefore[8];
                            holderBefore[8]     <= holderBefore[7];
                            holderBefore[7]     <= holderBefore[6];
                            holderBefore[6]     <= holderBefore[5];
                            holderBefore[5]     <= holderBefore[4];
                            holderBefore[4]     <= holderBefore[3];
                            holderBefore[3]     <= holderBefore[2];
                            holderBefore[2]     <= holderBefore[1];
                            holderBefore[1]     <= holderBefore[0];
                            holderBefore[0]     <= input_sample;
                            output_sample <= (input_sample + toAdd[0] + toAdd[1] +
                                              toAdd[2] + toAdd[3] + toAdd[4] + toAdd[5] +
                                              toAdd[6] + toAdd[7] + toAdd[8] + toAdd[9] +
                                              toAdd[10] + toAdd[11] + toAdd[12]);
                        end
                end
                endmodule

                • 5. Re: verilog base FIR filter madule
                  user_1377889

                  The very first errormessage reveals the incompatibility: There is no addressable memory in a datapath except a (very) few registers. So there probably is no chance to implement your algorithm in a datapath object.

                     

                   

                     

                  Bob

                  • 6. Re: verilog base FIR filter madule
                    kristopher.young

                    How many flip flops does this synthesize to in your quartus tool? PSoC5LP PLDs have only has 192 macrocells (flip flops). I don't think there's any way this can fit - especially the 13 16-bit coefficients (208 bits). I don't see the instantiation of mult1, but doing 16-bit multiplies in PSoC5 PLDs is prohibitive as well. The PLD logic in PSoC5LP is fairly limited when it comes to big functions like this. You can instantiate the datapaths to do some functions more efficiently (addition, subtraction, compares, shifts, CPU read/write access), but these do not synthesize out of straight verilog so you would have to write your verilog to instantiate them specifically and use the PSoC Creator UDB tool to configure them.

                       

                    Have you looked into using the digital filter block (DFB) via the filter component in Creator? The DFB is specialized DSP hardware in PSoC5LP that is made for doing this sort of thing.

                       

                    Regards,

                       

                    Kris

                    • 7. Re: verilog base FIR filter madule
                      user_14586677

                      The DFB assembler might be a good alternative -

                         

                       

                         

                          

                         

                               

                         

                      http://www.cypress.com/?rID=60720

                         

                      http://www.cypress.com/?app=forum&id=2492&rID=76907

                         

                       

                         

                       

                         

                       

                         

                      An FFT radar implemntation in PSOC 3 -

                         

                       

                         

                          

                         

                                http://web.mit.edu/balbekov/www/diy_coffee_can_radar.pdf

                         

                       

                         

                      Regards, Dana.

                      • 8. Re: verilog base FIR filter madule
                        soha.gh

                        thank's for your information.

                           

                        is there any were to implement FFT transfor or FIR filter with verilog based module?

                           

                        capabilty of psoc5lp is enough for this application?

                           

                        i want to disign a FFT processor with hardware description not a block with specific C code

                        • 9. Re: verilog base FIR filter madule
                          user_14586677

                          Try filterwizard@cypress.com, Kendall Castor Perry, if you find out anything

                             

                          post back for the forum users, I am sure there would be a lot of interest.

                             

                           

                             

                          Regards, Dana.

                          • 10. Re: verilog base FIR filter madule
                            soha.gh

                            ok

                               

                            I send email for him and i'm waiting for his reply

                               

                            thanks for your advices

                            • 11. Re: verilog base FIR filter madule
                              user_14586677

                              As far as doing a FIR or Comb filter in verilog, yes thats certainly doable.    

                                 

                              Note the DFB inherently does FIR, IIR.

                                 

                               

                                 

                                        http://en.wikipedia.org/wiki/Comb_filter

                                 

                               

                                 

                              Regards, Dana.