try to use temperature compensated quartz oscillator TCXO as frequency source to the PSoC5LP verilog based DDS. With 32bit or more e. g. 48 bit deep DDS accumulator you can easily achive 0.0000x Hz DDS resolution.
The typical osc circuit is two caps to create proper loading and
feedback. Pierce architecture.
You could consider connecting an additional cap to circuit and its ground
side to an open drain output. By controling the switching to the cap the effective
reflected Z will change, thereby changing the osc frequency. You would have
to experiment with this approach, and it potentially couple s clock noise into
the 32 Khz.
Another approach use a varicap controlled by a pwm followed by a LP filter to
generate bias, or a VDAC.
Just a thought, some possibilities.
For +/- 0.5hz, you need 15ppm, as you are compare two devices, that means your tolerance is now half, ie 7.5ppm.That means you need to use TCXO, but those TCXO seems to be more at mhZ range than 32khz.
thanks, DDS seems what I need. Can you give more info or link to how to DDS can be done on PSoC5LP?
The DDS approach achieves resolution via use of very high frequency
clock, and adds appreciable cost to the design, complicates board
certification for various standards, so some questions are
in order -
1) Do you need adaptive synch of clocks over T and V ?
2) Do you care about absolute accuracy of the two 32 Khz clocks, or just
need relative accuracy ?
3) Cost allowed for the solution part of this problem ?
DDS should give you the resolution you want. But the output still be affected by the stability of your clock souce.