As long as the voltage at the pin is between 0V and the VCC, it should be OK. Notice there are VCC to all 4 quardants of the chip.
You have to sequence Vdda first before Vddd if theyu are not the same.
GPIO are limited in spec sheet -
VCCD wont take long to rump up so if Vsignal is V1*1/2 all the time then you wont have any problem as long as V1*1/2 is lower than VCCIO and VCCIO is lower than VCCA/VCCD
In datasheet at "DC Specifications" recommended min value of VDDA is 1.8V, that's why I put second test case.
Use a DSO to establish timing of ramp to see if you are violating
Note bulk caps like tants and electrolytics have large C tolerances,
influence power ramp timing, and should be trialed at tolerance
extremes to make sure ramp of one supply will not be in violation
of chip specs.
pratik, if VDDA <1.8v , the PSOC might not work properly or might not work at all but it won't be damaged as long as there is no other higher voltage signal or power rail.