Answering my own question -- "Enable Multi-Slave mode" in the advanced tab is what does it.
Nope, un-answering my own question.
In UDB mode (i.e. for PSoC4 and 5LP), there is a "multi-master" mode which brings an OE signal out. My question was for the SCB SPI slave mode. Is there a definitive answer in the Cypress documentation or from someone here that states whether the SCB SPI slave MISO pin is tri-stated when the SCB SPI slave is not selected?
I got the same problem.
In SCB mode, the MISO pin appear to never goes in high-impedance. A simple solution is to put an external tri-state buffer.
Sorry, my bad...
The PSoC4 Cy8C4245AXI put the pin MISO in high impedance if the SS is not asserted. Work perfectly!