9 Replies Latest reply on Jun 5, 2014 3:24 PM by DaKn_263916

    HDLC Stack development



      I am  developing a HDLC stack based on the PSoC 5 on the Development kit. Amongst other functions, the controller must be able to to bit-stuffing/destuffing, be able to handle NRZI encoding and decoding schemes.


      Could anyone help with the start up of this design if you have any pointers.



        • 1. Re: HDLC Stack development

          I am no expert at all in this area, but my advice is to first understand what exactly you're really trying to do here. If your goal is to create a fully capable, fully compliant HDLC stack, you'll likely end up using all UDB resources, and your processor will be maxed out...meaning you likely won't have any resources left to do anything useful with the PSoC.


          Now, if you're trying to talk to a particular device, and if you know there is a particular subset of commands that will be used, then the PSoC will probably fit that bill nicely. I guess the real question is, what are you trying to do on the two ends? What do you envision the PSoC doing, aside from just processing the communcations stack? Are you monitoiring or controlling another device? Because frankly, if all you want to do is implement some kind of LAN protocol, you are far, far, far better off doing that in a CPLD or FPGA. The PSoC is a jack of all trades, and can do a lot, but it's the marriage of analog and digital that make it stand out. Using a PSoC to gather SCADA and transmit it over a LAN is a good use; just horsing around with a communications stack is not.

          • 2. Re: HDLC Stack development

            Thanx aviator. This is what i want to do. I'm not intending to design the full stack but i need a fraction of it. I need to recieved and decode the HDLC frame and then spit it put in serial format like RS232 and vice versa. The HDLC is coming from an PLC and i need to intepret the HDLC frame. i intend using the PSoC only for this and nothing else. so all the available resources can be channeled to the developolment of the hdlc.

            • 3. Re: HDLC Stack development

              Well, in that case, I'd say how you proceed would be based entirely with how comfortable you are doing Verilog versus C. It's a whole lot easier to do all of this in C, but the UDB is great at handling repetitive things like RLL if you are any good at Verilog coding.


              But, I maintain...if you have the development budget and Verilog or VHDL chops, program this kind of stuff into a CPLD. This kind of a project doesn't play to the PSoC's strengths, even though it certainly can be done.

              1 of 1 people found this helpful
              • 4. Re: HDLC Stack development



                I do understand. The problem is that i'm not strong with verilog and i do not have the resources to do that. Instead i have all the resources for the PSoC development. So i will need help on starting up with the PSoC and the building blocks for it if there is someone who has done something along these lines.





                • 5. Re: HDLC Stack development

                  If you can point me to a reference (or better yet attact a document) on the subset and commands of HDLC you intend to use, I could help you with some of this. Parsing most of the frame is something that could probably be done mostly in the UDB resources if not the DFB resources.


                  The only thing that concerns me at this point about this project is how you intend to do clock recovery and how you'd manage to keep the bit rate low enough for the PSoC to function...there's no way you'll reliably get more than 10 Mbit/s this way (whereas with a CPLD you could get a Gbit/s relatively easily).

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                  • 6. Re: HDLC Stack development



                    Find attached the block diagram for my intended design. What i need to do now is to make the building blocks for the two modules. Receiving and decoding as well as sending and encoding. Thanx for the heads up and insights.

                    • 7. Re: HDLC Stack development



                      I look for a microcontroller to replace SAB 82525 (production finished) with two HDLC channel. We use subset of the HDLC protocol and we want to change dynamicaly (during an initialization folow a configuration data after power on reset) a type of comunication interface. Either two SPIs with HDLC or two UARTs without HDLC.


                      I hope PSoC 7 would be fit for this task in future because we need an ethernet interface and four UART interfaces more too.


                      Presently I'd like to start this project with PSoC 5 and to make HDLC stack at first.


                      Could you help me?


                      Best regards


                      Ctirad Konecny

                      • 9. Re: HDLC Stack development

                        @konecc, if no one else replies consider filing a case to see if any work


                        is ongoing inside Cypress.








                        To create a technical case at Cypress -








                        “Technical Support”


                        “Create a Case”




                        You have to be registered on Cypress web site first.




                        Regards, Dana.