Answering my own question (again):
Looking at the Architecture TRM, Cypress gives a block diagram of the GPIO blocks. (section 19.2 on page 144 for the 5LP, for example). It specifically calls out the register names surrounding the MUX leading into the drive logic block. PRT[x]BYP controls whether the GPIO pin takes its output level from the DSI or the port's data register PRT[x]DR.
If the schematic symbol for the pin is already set up correctly you should not need to fiddle with the PRT[x]DM (drive mode) or PRT[x]BIE (bidirectional control) registers. Write the logic level you want to put on the pin to the correct bit in PRT[x]DM and flip PRT[x]DR bit to '0'. When you're done and want the peripheral to take over again, set the PRT[x]DM bit to '1' so the pin takes its logic level from the DSI.
The memory addresses for these registers is in the (very difficult to read) Register TRM.