5 Replies Latest reply on Aug 25, 2017 9:44 AM by userc_42420

    UDB Fifo read fails to raise empty flag

      My Intent: Develop a UDB datapath which compares values.  A byte is written into the Fifo F0 register via Software or DMA if it is empty, which clears the F0_Empty flag.  The written byte is then read into the datapath A0 register, which should raise the F0_Empty flag again, and compared to a pre-determined value.  If the value doesn't match it is written from the A0 register into the F1 register, which will trigger an external read via Software or DMA by raising the "Not_Empty" flag.


      Problem Statement: Moving the contents of the fifo F0 register into A0 via my udb state machine does not re-raise the F0_Empty flag.  It seems that when I read the data from F0 with A0 the read/write pointers are not updated, and thus neither is the status of the empty flags.


      I've Tried: I have confirmed that once written (in the very first state of my state machine), the F0_Empty flag goes from high to low as expected.  I have confirmed that the data I send makes its way into register A0, which means A0 is definitely retrieving the data as expected.


      Possible Areas of Concern: The Fifo's in the udb are 32 bits, could that mean that even if I only write 8 bits, there are 24 bits of zero padding being written into the Fifo, which incremented the write pointer by 4, and thus requires 4 reads to empty the Fifo?  This is the only thing I personally could think of, can anyone confirm this?


      I thought this information would be enough to get moving, but I've attached a copy of my workspace archive in case anyone was curious.  Thank you ahead of time for any help I recieve on this topic, I've been banging my head against a wall for 2 days now over this.

        • 1. Re: UDB Fifo read fails to raise empty flag

          Would it help to connect F0_Empty to .f0_bus_stat instead of .f0_blk_stat.





          • 2. Re: UDB Fifo read fails to raise empty flag

            Hi Bob, it's good to hear from you! I am not exaggerating when I say that you have helped solve MANY of my psoc problems over the past 3 years with your forum posts.  Flattery aside, I have attached a picture of the options I get in the UDB editor for the .f0_bus_stat and .f0_blk_stat.  I did not use the udb editor tool to write my verilog since it's a bit limiting, but I do use it to setup my UDB device, which I then copy and paste into my verilog to save time.  There it says that .f0_bus_stat means "not full".




            Also, the Component Author Guide (http://www.cypress.com/?docID=49650), on page 138, gives an explanation as to how those stats are defined. Since F0 is an input, .fo_blk_stat should indicate when F0 is empty.




            Sorry for the onslaught of information but I wanted to make sure I gave you enough information to verify this yourself so you didn't just have to take my word for it.  Thank you for your response, it gave me the idea to run a test where I place data in F0 and then read the status, and that way I can test how many bytes it takes until it becomes full.  My conclusion is 4 bytes, which answers the last question I posed in my original post.  However, reading from F0 with A0 still does not seems to affect the read pointer/empty flag.

            • 3. Re: UDB Fifo read fails to raise empty flag

              For those that may find this questions useful I have found a solution.  After looking through the PSoC Creator Training on Datapath FIFO, on page 4 there is a description of how Fifos are loaded and unloaded.




              This page pretty much states that the default location for Fifo F0 data to go is register D0, which is done through a logical expression in the instructions side of the udb editor, "OR" you can activate Fifo F0 as dynamic and you can use register A0 as your destination register (`SC_FIFO0_DYN_ON inside the UDB datapath configuration).  I tested both methods and they each clear the empty flag as expected.




              Thank you to Bob for taking the time to look at this for me.  It was by sheer luck that I found an article with the pertinent information in it, and even more lucky that I was in the frame of mind to correctly interpret what I was reading.  For any Cypress employee reading this, I think this information would be helpful if added to the UDB datapath component creator manual.  If it is already in there I apologize, its like 250 pages and extremely sparse, I must've read right over it.  Keep on PSoCing!

              • 4. Re: UDB Fifo read fails to raise empty flag

                I stopped using the datapath editor after a few tries realizing that some of the (required!!) signals were not accounted for. Now I'm waiting for the next version.
                The last UDB/DataPath problem I had was solved completely by creating a MyCase and supplying a well documented small source that produced the error. There are some DataPath Gurus at work at Cypress's I can assure you. It might take some time, but they will really help.


                On top of this page: Support&Community -> Technical Support -> Create a MyCase





                • 5. Re: UDB Fifo read fails to raise empty flag

                  Glad to hear that you soved your issue! I sent my previous post without having seen you last one, so skip that suggestion. Think I have to read something more...