Firstly, please not that CY7C1481BV25 is Not Recommended For New Designs. The closest alternative is CY7C1481BV33.
Thank you for your answer
Actually attached file is my schematic. I will notice your comments and I will do some Signal Integrity using provided IBIS model. But besides the termination part I'm not sure about Control and Enable Pins. Do I need Pull-up or Pull-down resistors on those signals ? (GW,CLK,CE1,CE2,CE3,OE,ADV,ADS,ADS,BWE,ZZ,MODE). I couldn't find out this from the datasheet.
I really appreciate it if you review the schematic file.
CY7C1481BV25.pdf 47.3 K
I reviewed the schematic and find that series termination is being used.
1. ZZ Pin has an internal pull down. For normal operation you can tie it to LOW or leave it floating.
2. MODE Pin has an internal pull up. So when left floating or tied to Vdd, it uses interleaved burst sequence.
You can add an external pull-up on all active low control signals. When the FPGA drives a LOW, the corresponding signal gets activated.
Even for the clock, you can add a Pull-Up resitior externally or directly drive the CLK from the FPGA.
Thanks and Regards