The data sheet does not explicitely tell that number. The best I can come up with is the input current into the inputs. For a normal GPIO, this is 2 nA. For a SIO inputs its 14nA, or 10µA when the input voltage is greater than Vddsio. From these numbers you can calculate the resistance (they are specified with a 3V input voltage).
Dear Rli ,
What is an SIO input. Please clarify whether it is same as an open drain input
SIO is a special kind of input pin. It allows for some special features to be enabled (e.g. higher output drive, ability to handle input voltages higher than supply voltage). Both normal and SIO pins can be set to open drain.
Maybe I suggest you read the PSOC5LP data sheet, and the architecture reference manual (TRM) for the PSoC5LP, there all the details about the different pin types is explained.
dear hli ,
Thanks for the clarification. so can I take the resistance in the high impeadance state to be 3V/10nA. = 300 Meg ohms?
The 2 nA is room temp only, max, and not production tested.
Impedances like this, 10's of megohms and higher, are very subject to
board layout, contaminants, surface treatment........Then you have AC issues,
eg C coupling to pins in Hi Z state........
If you describe further what you need for loading, circuit issues, etc.., maybe we can help you further.
But the 2nA figure is still true for the PSoC. Its independent of what you are doing with the board 8and yes, getting to below 2nA leakage current there will be tricky).
The 2 nA is a max value at room temp, not tested in production. But
that leakage is only part of the problem trying to achieve these levels
of Z in a design. Taken in isolation the leakages of PSOC only part
of the design issues. Routing and attached parts and temp a big
factor in Hi Z designs. Everything is important.
I did the following test with the PSoC pin in open drain pull down mode.
First I put the open drain pin in high impeadance mode then I used an external current source to input a constant current.
I sourced a current of 10 nano amperes into the pin.
I measured the voltage developed on that pin. The measured voltage was exactly 1 V with respect to VSSA/GND.
So from these observations I conclude that the channel resistance offered by an open drain pin in the high impeadance mode is around 10 Megohms.
Please provide comments, corrections / suggestions if any
Have you consider the impedance of your measuring equipment. For such a high impedance situation, the measuring tools impedance would affect the reading.
You have to be careful here as measurement of high Z generally means
you use a DVM with line filter rejection capabilities. Also could you have
been measuring the complient limit of your current source ?
In so far as what you measure, the leakage on a pin, is a f( T, contaimanents,
second order V effects....) and is not production tested (due to settling time
to take a measurement hence test time). It is a combination of layout leakage,
diode leakage, MOSFET leakage, ESD protection circuits......
So if you truly need very high Z guarenteed you may have to do that off chip with guards.
What is driving your need for the hi Z, target for Z.....?
I want to use the High Z for holding charges on a capacitor. Whenever I want to discharge the capacitor I would pull down the capacitor terminal to ground.
So you need something like the Sample&Hold-Component available in Creator?
What capacitance are we talking about, and how long should it hold its charge? Are you sure the self-discharge current of the capacitor is lower than the PSoC leakage current?
As HLI points out you have to answer for your design several questions -
1) Storage time
2) Acquistion time
Of course you can always do this digitally, measure the pin voltage with DelSig, and store it in EEPROM
almost indefinitely with no concerns for temp, capacitor quality, aging, ancillary leakages......You can reporduce the
voltage with VDAC or if more resolution needed PWM followed by LPF.
Until we know more about goals, what you are trying to accomplish, we cannot assist you furthur.