If timing is crucial Verilog solution would of course effect this easily.
If timing not that critical nothing more than a one shot timer counting out
n timing cycles and driving a gate/FF would suffice.
the design-wide clock I'm trying to get out of the device is used internally to synchronize data coming in to the device that is being clocked by that same clock.
I ended up with a negative-edge-triggered FF to create a glitch-free clock enable. I haven't tested it yet:
SWD_DONE goes high when 46 clock cycles have elapsed and stays high until the counter is reloaded. I use a negative edge triggered flip flop to ensure the first rising edge is seen.
clken.png 11.9 K