4 Replies Latest reply on Aug 7, 2014 6:01 PM by user_275099341

    Psoc5 DMA 64K page limit

    user_342849713

       Good morning everyone from Spain,

         

      Here's a tricky problem, I need to fill (nearly) an 8Mbit RAM (1Mx8) with incoming ADC data before processing it. As I was reading the DMA specs, it seems that there's a 64K page limit, ie the 16 higher bits don't get increased when the lower 16 bits roll from FFFF to 0000.

         

      Is there an efficient way to overcome this?? I have though of a HW solution which could be nice, I prefer not to use interrupts... but hey maybe someone can come up with a better solution!

         

       

         

      Regards,

        • 1. Re: Psoc5 DMA 64K page limit
          user_44074550

          Hi Enrique33,

             

          to find and test the solution I need to know the connection of your 8Mbit RAM (1Mx8). Please can you publish your schematics.

             

          Regards, 

             

          Viktor

                                                                 
                                                                                                                    
          Enrique33 posted on 11 Apr 2014 12:20 AM PST 
          Member 
          3 Forum Posts
           
           

           Good morning everyone from Spain,

          Here's a tricky problem, I need to fill (nearly) an 8Mbit RAM (1Mx8) with incoming ADC data before processing it. As I was reading the DMA specs, it seems that there's a 64K page limit, ie the 16 higher bits don't get increased when the lower 16 bits roll from FFFF to 0000.

          • 2. Re: Psoc5 DMA 64K page limit
            user_78878863

            First note: the DMA can do only 4095 bytes (yes, thats right, its not 4096...) per single transaction. So you need to handle that first.

               

            To get more than 64k of transfer, you can used an indexed / chained DMA configuration: http://www.cypress.com/?rID=39408&cache=0

               

            That way you can modify the TD automatically.

               

             

               

            hli

            • 3. Re: Psoc5 DMA 64K page limit
              user_342849713

               dvorakvik, the schematic is pretty simple, an aynchronous EMIF component (24 bit addr, 8 bit data),an external SRAM 1Mx8,  and an external 8 bit ADC connected to a Psoc Port.

                 

              I'll have to look more deeply into it but the Indexed DMA will probably do.

                 

               

                 

              thanks

              • 4. Re: Psoc5 DMA 64K page limit
                user_275099341

                Am I right -- indexed DMA is impossible on PSOC5 in a single TD chain when destination is SRAM, since HI16 of SRAM address and TD (0x400..... base) address is different?