1 2 Previous Next 15 Replies Latest reply on Aug 11, 2014 12:04 AM by user_1377889

    I2C Problem with 8C24123




      I am attempting to get two 8C24123 PSOC 1's to communicate over I2C.


      On the master, using I2Cm (called MOTOR) , I init as follows


        M8C_EnableIntMask(INT_MSK0, INT_MSK0_GPIO);






      I then send data as follows


      BYTE CS = speed + MOTOR_ADDRESS;


      BYTE data[3];




      data[0] = speed;


      data[1] = 0;


      data[2] = CS;




      MOTOR_bWriteBytes(MOTOR_ADDRESS, data, 3, MOTOR_CompleteXfer);




      On the slave PSoC, I use the EZI2Cs (called I2C) and init as follows


      struct I2C_regs




      BYTE data[3];


      BYTE shadow;


      } MyI2C_Regs;




      MyI2C_Regs.data[0] = 0;


      MyI2C_Regs.shadow = 0;




      I2C_SetRamBuffer(4,3,(BYTE *)&MyI2C_Regs);










      Then I just check for data values in loop 




      while(1) {


          // do some checks on MyI2C_regs.data[0]






      The MOTOR_ADDRESS is 0x60


      The attached lower image shows the PSoC to PSoC communication. The slave PSOC acks the Write request to address 0x60, but it Naks the first byte written (0x46) and the communication ends. I also never detect data[0] as being 0x46 on the slave (as if the data has not been passed from the EzI2C routines to the ram location).


      On the upper image, I am using the Microchip PicKIT serial analyser as the slave, with the PIC kit set to slave mode and address 0x60. In this case, the PicKIT NAK's (or ignores) the write to slave 0x60 from the master.


      I usually do the same sort of communications from a 8C29466 as the master with 8C24123 as slave and the 123 slave code has worked fine in the past.


      All the SCL/SDA pins are Open Drain Low mode. Pull ups are 4K7


      Does anyone know why this may not be working correctly?





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