11 Replies Latest reply on Aug 11, 2014 4:49 AM by DaKn_263916

    External bypass cap for SAR in CY8CKIT-001

      Hello All,


      I am using CY8CKIT-001 development board. Currently am working with SAR ADC of PSoC 5LP. As per data sheets in order to go for sample rates beyond, 100 000 sps, I need to go for Internal reference bypass mode in which, I need to externally connect a capacitor on either pin P0[2]  or P0[4] for SAR1 and SAR0 respectively.


      What I need to know is whether this capacitor is already installed in the dev board or do I need to externally install it? My intial investigations tells that this is not on the board. Anybody who has used SAR in high sample rates can help me in this regards.



        • 1. Re: External bypass cap for SAR in CY8CKIT-001

          P0_2 and P0_4 are braught out on connector P19. There are no caps installed, neither on the motherboard nor on the processor module.





          • 2. Re: External bypass cap for SAR in CY8CKIT-001

            The association of SAR 0 and SAR 1 and external pins is -




            External Vref  Uses an external reference on pin P0[2] for SAR1 or on pin P0[4] for SAR0.




            Normally I would recommend a poly tant for bypass as it has ~ 10X better f vs ESR curves


            than a regular tant. However using the ohmmeter tool it states path R from SAR ext ref internal


            connection to P0_4 is ~ 2,000 ohms. Which seems very high to me, stated another way not


            sure how much a cap would help with a typ ESR in that freq range, eg. the path R dominates.


            So I will file a CASE on this to see if the 2K ohm measurement is legit.




            Regards, Dana.

            • 3. Re: External bypass cap for SAR in CY8CKIT-001

              Dear Bob,


              Thanks for the straight forward answer.


              Dear Dana,


              Thanks for answering.





              • 4. Re: External bypass cap for SAR in CY8CKIT-001

                Have received a partial answer from tech support on tool descrepancy.


                Cypress agrees there is some error in ohmmter tool with respect to this


                Vref measurement path.




                I will keep posted when I get final answer.




                Regards, Dana.

                • 6. Re: External bypass cap for SAR in CY8CKIT-001



                  Sorry for the last empty post. I tried to reply using Chrome, that was the problem I guess.


                  As mentioned earlier in this post, I am working with SAR ADC at higher data rates, beyond 100k sps which need to mive for the internal refernce bypass mode.
                  I am using SAR1 with external capacitor attached to P0_2.


                  Here are my current confugurations.
                     Sample rate: 1000000
                     Input Range: Vsaa to Vdda (Single Ended)
                     Reference: Internal Vref, bypassed
                     Sample mode: Software Trigger
                     Clock source: Internal


                  When reading the ADC value below are the steps am following.












                  voltageADCPixel = ADC_SAR_1_GetResult16();










                  In order to have proper operation are there any other steps I need to follow?
                  Please advice.



                  • 7. Re: External bypass cap for SAR in CY8CKIT-001

                    Since 1 million samples per second is quite a lot you might get near the processor's MIPs limit. You could consider reducing CPU load by using DMA but to suggest you anything helpful, it would be advisable to tell us what you intend to do with the ADC'd values.


                    How long will the measure be performed ? Infinity or a burst of ??ms


                    What do you use the values for?  Streaming out? What interface?


                    Are you filtering the data?





                    • 8. Re: External bypass cap for SAR in CY8CKIT-001

                      The 5LP is ~ 100 DMIPS when run at 80 Mhz.




                      SAR max conversion rate is ~ 1 MSPS.




                      Regards, Dana.

                      • 9. Re: External bypass cap for SAR in CY8CKIT-001



                        Thanks for replies.
                        Even with lower sampling rates the issue persists.
                        ADC measurements are taken repetitively, once 4/5 ms.
                        Measured ADC values are sent to PC using UART.


                        Observing the received data on PC I see the resulted ADC values for a constant input voltage varies largely, around 100 ADC counts. This suggests that the ADC reference is not stable in this mode (Internal Vref, bypass). Any suggestions to make this stable. System seems to be somewaht ok with external Vref. Is it possible to achive the stability of External Vref, with Internal Vref, bypass mode?



                        • 10. Re: External bypass cap for SAR in CY8CKIT-001

                          I have a CASE filed about the bypass effectiveness. So far I


                          have learned that P3_7 has a 300 ohm route burden, and


                          P0_4 at 2000 ohms per ohmmeter (this is being looked into


                          as well) to the internal Vref bypass point.




                          I would start using DSO on infinite persistence and establish


                          basline of noise in system. Then using triggering outside CM range


                          look for specific trouble spots.




                          Use polymer tantalums in lieu of regular tants, they give you an order


                          of magnitude better Z vs f performance. And of course MLCs for the


                          hi freq stuff.




                          Consider turning off other peripherals when you do the measurements.








                          http://www.cypress.com/?rID=39677     AN57821 - PSoC® 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations


                          http://www.cypress.com/?rID=40247     AN58827 - PSoC® 3 and PSoC 5LP Internal Analog Routing Considerations


                          http://www.cypress.com/?rID=39974     AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs






                          Regards, Dana.

                          • 11. Re: External bypass cap for SAR in CY8CKIT-001

                            Final answer from Cypress tech support -








                            Hi Danaa,




                            The resistance value shown by ohmmeter in analog viewer is 'not correct'.




                            I did speak to the design team and verified that-




                            The route from the internal reference voltage to the by-pass cap pins are 'kelvin' connection and have a routing resistance of apprx. 20 to 30 ohms.




                            The value shown by Creator is not correct for the dedicated routes, but other routes via globals and mux buses.




                            I have filed an internal ticket to fix this issue in our next release. I apologize for our mistake. Sorry for the inconvenience.




                            Please let me know if you have any concerns.