2 Replies Latest reply on Aug 12, 2014 9:53 AM by userc_42325

    Ganging nvSRAMs, vswitch threshold tolerance

    userc_42325 Aug 12, 2014 9:53 AM

       I am working on a design using five STK14CA8 devices.  These are ganged to make up a 32bit bus plus a 4th byte for syndrome bits - so 40 bits wide total

         

      The design uses pullups on WE CE OE and HSB (10K)

         

      HSB is ganged between all devices, pulled up, and routed to my system controller

         

      There is one VCAP, also ganged to the 5 devices

         

      The value of the capacitor (VCAP) is 5 times larger to accomodate for the fact that there are 5 devices 

         

       

         

      Here is my problem:

         

      I have 5 samples (out of hundreds produced) where one of the 5 chips (usually lane 0) gets corrupted in the field.  It seems that the entire device is in a random state.  Reloading corrects the issue, and I can't reproduce the problem on any "failed" board.  Customers want to know why it failed.

         

      Questions,

         

      1.  If you gang the devices, what will happen if the Vswitch is slightly different from device to device ?  Cap discharge is exponential, and if you switch in a device later, after VCAP starts discharging, won't that upset the auto store because it changes the slope of the discharge radically ?  Why is there no typical, min and max for vswitch value ?  They can't possibly all be the same across all devices produced can they ?

         

      2.How much time passes from the crossing of vswtich to the inhibit of reads and writes ? Can this truly be zero as the datasheet implys ?

         

      3. Why is there no mention of ganging devices in the datasheet - it seems like you CAN NOT DO THIS, at least reliabily.  Any opinions there ?  (one member says yes you can - but why do you think that ?)

         

      4.  It also seems strange that Cypress took off the mention of ganged HSB in their last rev.  Is that because you can't do it ?

         

      Thank you

      • 104 Views
      • Tags:
        • 1. Re: Ganging nvSRAMs, vswitch threshold tolerance
          ravip_ Aug 11, 2014 7:17 AM (in response to userc_42325)

          HSB pin ganging is not recommended in STK14CA8 (which is a 0.25 micron technology part that was made obsolete 3 years back). In the current generation 0.13 micron 1Mb nvSRAM part CY14B101LA, ganging is allowed. I have placed the reasons in the responses to your numbered questions.

             

          #1. You are right that the VSWITCH is not the same in all devices. However,  please note that the VCAP specified is such that it can supply the AutoStore current for the duration of the store time in worst case conditions. Since you have increased the ganged VCAP to 5 times of what is recommended for a single device, it does not matter when each part goes into AutoStore. The charge in the capacitor will be sufficient to provide store current for the 5 devices irrespective of whether all the devices start store at the same time or if each device starts store at different times. 

             

           

             

          #2:   Yes, I/Os get inhibited immediately when VCC crosses VSWITCH. Since VSWITCH level is a max level, application should ensure that read writes are not done below 2.7V.  If you continue to write, then the data written into the different devices will be different since each device will continue to write until its VSWITCH is crossed. 

             

          #3: In STK14CA8 HSB ganging should not be done. This is because a LOW on the HSB pin input will internally pull the HSB pin LOW - when there has been a write to the SRAM, HSB will stay LOW for the store cycle duration and when there has been no write to the SRAM, HSB will still be pulled LOW internally for tDELAY time. Therefore, when parts are ganged, a HW store initiated by pulling the HSB pin LOW can hold the HSB pin LOW indefinitely. The device which completes the store first will release the HSB pin but the other devices are holding the pin LOW. For the first device, this is a condition of HW store where no write has occurred. Internally, its HSB pin gets pulled LOW for tDELAY time. This can go into a loop with each device initiating a HW store in the other devices. In CY14B101LA, this will not happen since a LOW on HSB will not pull HSB LOW internally when there has been no write to the SRAM. Hence ganging of HSB is allowed in the case of CY14B101LA. However, please note that AutoStore disable feature should not be used when ganging. This is because, when the HSB pin of the device with higher VSWITCH goes LOW during power down, it could initiate a HW store in the device for which VDD has not crossed VSWITCH.

             

           

             

          #4. Ganging is allowed in STK14C88 which is an older, 0.8 micron technology part and not in STK14CA8. Hence ganging was never recommended in STK14CA8.

                                Regards   

           

             

          Ravi

             

          Cypress Applications

          • 2. Re: Ganging nvSRAMs, vswitch threshold tolerance
            userc_42325 Aug 12, 2014 9:53 AM (in response to userc_42325)

             Very good.  Thank you for the explanation.  It is most appreciated !