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Wanted to know if someone had the information.
Will keep this post up-to-date as soon as I receive the info from the technical support.
Cypress gave me a part of the answer. It may go up to 8MHz. For better linearity you have to use it at 2.67MHz and lower.
Even thats odd. They show in specs 2 Mhz to achieve those specs in
spec table. But then throw out another value (2.67) and did not clearly
state what performance you would get. What is it about 2.67 that is
worth paying attention to ?
I think the 8 Mhz not unusual, but should have had specs associated with it.
And then a set of specs attached to the 2.67....
Food for thought, Dana.
Sorry about it you are right they told me 2MHz
All these specs come largely from characterization data built up
from initial production runs. Hopefully Cypress will update datasheet
with, at minimum, data to support spec clock rates.
PSoC ADC specs are done at 2.0 MHz because it is the highest frequency where performance can be guaranteed to the specified number of bits .... and this is important . . . . over all combinations of process variation, voltage and temperature.
Most (that's not a quantitative number) of the time, you could run at higher frequency, but Cypress can not GUARANTEE that it will work over P, V, and T. Logically, lower resolution will allow you to run at higher clocks because the opamp settling requirement is not as bad. What falls apart when clock exceeds the power limit are INL and DNL.
I requested years ago that we characterize ALL of the ADCs over clock vs resolution vs power. What I came up would have taken several thousand man-hours. This is not practical. There is some useful guidance here. The speed of the opamp varies directly with the power setting, so that an ADC at P=H, B=H and 2.0 MHz clock will have the same INL and DNL performance as P=H, B=L and 1.0 MHz clock. What changes is the data rate.
If you need speed and resolution in PSoC1, use the DelSig ADCs. If 10 bits is enough, CY8C28xxx has a 10 bit SAR converter with enough speed to overload the computational pipeline.
As is said in AN2239 DualADC and TriADC are both an expended version of ADCINCVR. Those two datasheet specify that the DataClock is up to 8MHz with minor difference in DNL compare to ADCINCVR.
I'm not saying that the datasheet of DualADC or TriADC may be used as such for ADCINCVR but that it is ackward that a module that is an extension of the first one allow the user to go higher in frequency.