3 Replies Latest reply on Feb 4, 2014 9:29 AM by raul.rangel

    problem with Repeated data in FX2LP

    james.farm

      hi

         

      i want send data from fpga to pc with maximum rate.i use this vhdl code & FX2LP frimware slave fifo mode

         

       

         

      //////////////////////FX2LP frimware slave fifo mode///////////////////////////////

         

       

         

         

       void TD_Init( void )
      { // Called once at startup

        CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT
      //  FIFOPINPOLAR |= 0x03;

        PINFLAGSAB = 0xE0;            // FLAGB - EP6FF
        SYNCDELAY;
        PINFLAGSCD = 0x08;            // FLAGC - EP2EF
        SYNCDELAY;
        PORTACFG |= 0x80;
          SYNCDELAY;
        IFCONFIG = 0x03; //external 48mhz clock from fpga to fx2 ifclk pin
        SYNCDELAY;

            CPUCS |= 0x02;

        EP2CFG = 0x02;                //out 512 bytes, 4x, bulk
        SYNCDELAY;                    
        EP6CFG = 0xE0;                // in 512 bytes, 4x, bulk
        SYNCDELAY;              
        EP4CFG = 0x02;                //clear valid bit
        SYNCDELAY;                     
        EP8CFG = 0x02;                //clear valid bit
        SYNCDELAY;   

        SYNCDELAY;
        FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
        SYNCDELAY;                    // see TRM section 15.14
        FIFORESET = 0x02;             // reset, FIFO 2
        SYNCDELAY;                    //
        FIFORESET = 0x04;             // reset, FIFO 4
        SYNCDELAY;                    //
        FIFORESET = 0x06;             // reset, FIFO 6
        SYNCDELAY;                    //
        FIFORESET = 0x08;             // reset, FIFO 8
        SYNCDELAY;                    //
        FIFORESET = 0x00;             // deactivate NAK-ALL

        SYNCDELAY;                    //
        EP2FIFOCFG = 0x00;            // AUTOOUT=0, WORDWIDE=1
       
        SYNCDELAY;                    //
        EP2FIFOCFG = 0x11;            // AUTOOUT=1, WORDWIDE=1
       
        SYNCDELAY;                    //
        EP6FIFOCFG = 0x0D;            // AUTOIN=1, ZEROLENIN=1, WORDWIDE=1

        SYNCDELAY;

          
      }

         

      ///////////////fpga vhdl code/////////////////////////////

         


      PROCESS(CLK_OUT1,reset_n)
      BEGIN
      IF RISING_edge(CLK_OUT1) then

      case state is

      when 0 =>

      slwr_n<='1';
      faddr <= "10";
      state<=1;
      when 1=>
      if flag_b='1' then
      state<=2;
      else
      state<=1;
      end if;
      when 2=>
      fdata <=fdata+1;
      state<=3;
      when 3 =>
      slwr_n<='0';
      state<=1;
      end case;
      end if;
      end process;

         

      this vhdl code product incremental numbers and send it to FX2LP but  there is a problem in my recieved data by "usb control center" some data's are Repeated several times.why ?

         

      I open this data with malab.in shape the line must be right but it is

         

       

         

      BULK IN transfer
      0000 EC 10 ED 10 EE 10 EF 10 E0 10 E1 10 E2 10 E3 10
      0010 E4 10 E5 10 E6 10 E7 10 E8 10 E9 10 EA 10 EB 10
      0020 EC 10 ED 10 EE 10 EF 10 00 11 01 11 02 11 03 11
      0030 04 11 05 11 06 11 07 11 08 11 09 11 0A 11 0B 11
      0040 0C 11 0D 11 0E 11 0F 11 00 11 01 11 02 11 03 11
      0050 04 11 05 11 06 11 07 11 08 11 09 11 0A 11 0B 11
      0060 0C 11 0D 11 0E 11 0F 11 20 11 21 11 22 11 23 11
      0070 24 11 25 11 26 11 27 11 28 11 29 11 2A 11 2B 11
      0080 2C 11 2D 11 2E 11 2F 11 20 11 21 11 22 11 23 11
      0090 24 11 25 11 26 11 27 11 28 11 29 11 2A 11 2B 11
      00A0 2C 11 2D 11 2E 11 2F 11 40 11 41 11 42 11 43 11
      00B0 44 11 45 11 46 11 47 11 48 11 49 11 4A 11 4B 11
      00C0 4C 11 4D 11 4E 11 4F 11 40 11 41 11 42 11 43 11
      00D0 44 11 45 11 46 11 47 11 48 11 49 11 4A 11 4B 11
      00E0 4C 11 4D 11 4E 11 4F 11 60 11 61 11 62 11 63 11
      00F0 64 11 65 11 66 11 67 11 68 11 69 11 6A 11 6B 11
      0100 6C 11 6D 11 6E 11 6F 11 60 11 61 11 62 11 63 11
      0110 64 11 65 11 66 11 67 11 68 11 69 11 6A 11 6B 11
      0120 6C 11 6D 11 6E 11 6F 11 80 11 81 11 82 11 83 11
      0130 84 11 85 11 86 11 87 11 88 11 89 11 8A 11 8B 11
      0140 8C 11 8D 11 8E 11 8F 11 80 11 81 11 82 11 83 11
      0150 84 11 85 11 86 11 87 11 88 11 89 11 8A 11 8B 11
      0160 8C 11 8D 11 8E 11 8F 11 A0 11 A1 11 A2 11 A3 11
      0170 A4 11 A5 11 A6 11 A7 11 A8 11 A9 11 AA 11 AB 11
      0180 AC 11 AD 11 AE 11 AF 11 A0 11 A1 11 A2 11 A3 11
      0190 A4 11 A5 11 A6 11 A7 11 A8 11 A9 11 AA 11 AB 11
      01A0 AC 11 AD 11 AE 11 AF 11 C0 11 C1 11 C2 11 C3 11
      01B0 C4 11 C5 11 C6 11 C7 11 C8 11 C9 11 CA 11 CB 11
      01C0 CC 11 CD 11 CE 11 CF 11 C0 11 C1 11 C2 11 C3 11
      01D0 C4 11 C5 11 C6 11 C7 11 C8 11 C9 11 CA 11 CB 11
      01E0 CC 11 CD 11 CE 11 CF 11 E0 11 E1 11 E2 11 E3 11
      01F0 E4 11 E5 11 E6 11 E7 11 E8 11 E9 11 EA 11 EB 11
      BULK IN transfer completed