Can you post schematic and project, so we don't have to guess
how you have configured and what external interface looks like.
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What do you mean by "the voltage readings drop"? Does the signal you measure change? Do you just measure aa voltage that is too low? For signals that span from GND to Vdd you need to configure the ADC input buffer proeprly - look at the data sheet for that.
the configuration of the ADC where given by our professor so we only know a little bit on it. the level shifter compresses the voltage from the main circuit from -14 volts to 14 volts into a 0 to 5 volts ratio. i posted the schematic of the circuit an the configuration of the adc.
schem.JPG 175.9 K
There are several considerations here -
1) With A/D configed with input buffer on you can see by graphic it cannot
range from gnd to Vdd, eg. its common mode range is NOT rail to rail.
2) You can config input buffer off, then input CM range exceeds 0 - Vdd,
however A/D input Z drops to 74 K (for 16 bits) which then upsets the
level shifter / divider in schematic, R11/12/13. So you would have to calc
new values for them.
3) The actual V at input to PSOC is level shifted and attenuated by R11/12/13.
That is reason voltage drops when referred to OP27's output.
thank you for your help i'll try to do all of your suggestions