Npo, the report file should have the information from the last build you run. So it shows you were it tried to put stuff, and which resources are used.
Were to look for optimization:
- usage of fixed-function components instead of UDB components
- configuring the UDB components to use less UDBs - for that, look into the data sheet, it shows the resource usage
- be careful with glue logic and registers - they might hog resources
I could come a bit nearer to 2 blocks short by removing the digital-io control registers. that would require a change in program and writing to the pins directly using a shadow register.
I am not sure what your ss-logic with the ored outputs is good for, possibly something that can be done in software, too.
Shadow registers apply to PSOC 1, PSOC 3 pin APIs take care of
the Read modify Write problem on GPIO.
I was talking about shadow registers to have the ports switched synchroneously which else may affect the external hardware.
A Port_1_Write() followed a few µs by a Port_2_Write() may have side-effects I cannot see from the schematic. Since originally the ports are switched simultaneously I thought this to be a safer solution.
In my design, all of the SS lines which exit the chip are controlled by software. The hardware SS lines from the Flexible_SPI components are ANDed together to detect when they have all finished their transactions.
Please find attached the contents of my .RPT file. What can I learn from it. It doesn't seem to say anywhere that I have exceeded 100% capacity on any particular resource.
103-000-2006-01.rpt.zip 27.8 K
You should inspect the .rpt- file from your original (working) design. The .rpt of the non-fitted design does not reflect what did not fit into into the device, but only what fitted so far.
The difference between your chips is the number of UDBs (24/20). Part of an UDB are 2 PLD (Programmable logic) blocks.
The already reduced design (Control Registers) still needs 43 PLD-blocks and only 40 are availlable.
When you can reduce some of your used logic you can succeed, some FFs, some gates...
When I switch back to the 027 device with 24 UDBs, I can compile the project. This is what the .RPT file says:
Resource Type : Used : Free : Max : % Used
Digital clock dividers : 8 : 0 : 8 : 100.00%
Analog clock dividers : 1 : 3 : 4 : 25.00%
Pins : 47 : 1 : 48 : 97.92%
UDB Macrocells : 111 : 81 : 192 : 57.81%
UDB Unique Pterms : 211 : 173 : 384 : 54.95%
UDB Total Pterms : 224 : : :
UDB Datapath Cells : 11 : 13 : 24 : 45.83%
UDB Status Cells : 17 : 7 : 24 : 70.83%
Status Registers : 1
StatusI Registers : 14
Sync Cells : 7 (in 2 status cells)
UDB Control Cells : 10 : 14 : 24 : 41.67%
Control Registers : 5
Count7 Cells : 5
DMA Channels : 10 : 14 : 24 : 41.67%
Interrupts : 3 : 29 : 32 : 9.38%
DSM Fixed Blocks : 1 : 0 : 1 : 100.00%
VIDAC Fixed Blocks : 0 : 4 : 4 : 0.00%
SC Fixed Blocks : 0 : 4 : 4 : 0.00%
Comparator Fixed Blocks : 0 : 4 : 4 : 0.00%
Opamp Fixed Blocks : 0 : 4 : 4 : 0.00%
CapSense Buffers : 0 : 2 : 2 : 0.00%
Decimator Fixed Blocks : 1 : 0 : 1 : 100.00%
I2C Fixed Blocks : 1 : 0 : 1 : 100.00%
Timer Fixed Blocks : 0 : 4 : 4 : 0.00%
DFB Fixed Blocks : 0 : 1 : 1 : 0.00%
USB Fixed Blocks : 0 : 1 : 1 : 0.00%
LCD Fixed Blocks : 0 : 1 : 1 : 0.00%
EMIF Fixed Blocks : 0 : 1 : 1 : 0.00%
LPF Fixed Blocks : 0 : 2 : 2 : 0.00%
Where in the .RPT file can I see the number of PLDs used?
PSoC implements programmable logic through an array of
small, fast, low-power digital blocks called Universal
Digital Blocks (UDBs). PSoC devices have as many as 24
UDBs. As shown in Figure 1, a UDB consists of two small
programmable logic devices (PLDs), a datapath module,
and status and control logic.
Each UDB you place lists the resources it uses in the datasheet
for that component,
"Where in the .RPT file can I see the number of PLDs used?"
A little bit further down, look (or search) for "PLD Packing Summary"