1) Is that because VDAC pin is HiZ as default ? And not terminated in any
load that can absorb the leakage ?
2) What is the concern over this pin developing a voltage ?
2) The VDAC is connected to a transistor current source and i run into problems if i get the maximum current in my device while programming
1) well i understand, but is there an possibility to change this?
While programming the PSOC GPIO, not having been configured during
boot, must be Hi Z digital. I have to check on this. What is the schematic
look like for the external current source, are you seeing enough leakage
from a Hi Z pin to create the problem ?
What is the range of current created by your external I source ? Maybe you
could use a GPIO to turn on its ground path once PSOC starts up ?
From ap note AN72382 -
Startup and Low-Power Behavior
Out of the box, all GPIO pins start up in an Analog HI-Z
state, where they remain until reset is released. The initial
operating configuration of each pin is loaded during boot
and takes effect at that time. You can change the reset
behavior of GPIOs using the PRTxRDM fields of the
nonvolatile latch array, which are written when the PSoC