Consider the DFB Assembler, that allows you to control
a single cycle MAC and would be a natural for your re-
Note any recomendation is highly dependent on some other
questions, like what is the speed you need for the counter ?
You can do that in VeriLog, but that is a bit challenging for a beginner. There is a "Component Author Guide" referring to verilog and a verilog guide already installed in your Cypress folder. Additionally some videos will guide you, look here:video.cypress.com/video-library/search/verilog/
Thanks for the quick replies.
I'm trying to run at BUS_CLK (32MHz), as the counter En is driven from a TERMOUT signal, and the COUNTER value gets read by a different DMA (64-2080 cycles later).
I've started playing with the UDB Editor and have a small component that I'm trying to test.
Did also create one Verilog component as an example.
Just wanted to check I wasn't looking over a more obvious solution.