10 Replies Latest reply on Oct 26, 2014 10:44 PM by user_343349849

    Problem with Digital output timing

    user_343349849

       Hi,

         

      I am working on a project that needs to toggle an "H" Bridge at 125kHz.

         

      If I drive just one output pin on and off I get the exact same ON and OFF period. When I add a second drive pin the ON time gets longer than off time for some reason. I have attached the bundle for the project. It just uses NOPs to create delay for on and off (I am not sure how accuracte the cyDelayus routine is).

         

      If I uncomment NMOS1 only, I get 8us ON time and OFF time. If I comment out NMOS1 and use NMOS2 I also get 8us ON time and 8us OFF time. If I use Both then I get 10.7us ON time and 8us OFF time for BOTH.

         

      The program needs to set P1/ N2 for the first 1/2 cycle and P2/N1 for second half with symettrical 4us period. (During each half cycle it switches off the unused pairs of control)

         

      Thanks

        • 1. Re: Problem with Digital output timing
          user_1377889

          David,

             

          you can rely on the CyDelay() function as you can rely on the clock precision.

             

          What you like to do, getting a precise timing for your h-bridge, could be done best with some hardware state-machines using LUTs. When a project using delay-functions gets expanded there will be the need for serving interrupts which will destroy any exact software-timings. Making sure that the bridge does not generate a shortcut can be done best in hardware.

             

           

             

          Bob

          • 2. Re: Problem with Digital output timing
            user_1377889

            Additionally some infos you get when typing "h bridge" into the keyword search field on top of this page :-)

               

            www.cypress.com/

               

             

               

            Bob

            • 3. Re: Problem with Digital output timing
              user_14586677

              This is one case where I would advocate external integrated H Bridge,

                 

              like Infineon, TI, Freescale, Intersil, IR....

                 

               

                 

              Reason is these have thermal protection, extensive OV protection,

                 

              gate drivers, high currents due to gate drive and drain loads are

                 

              internally routed to allow easy board layout, translate ground transients

                 

              due to layout minimized. Also timing due to component differences better

                 

              controlled and screened.

                 

               

                 

              www.google.com/url

                 

               

                 

              Essentially these integrated parts become just a simple logic PWM interface

                 

              from PSOC.

                 

               

                 

              You can even get parts that are galvanicaly isolated, eg. medical applications, etc..

                 

               

                 

              Regards, Dana.

              • 4. Re: Problem with Digital output timing
                user_343349849

                 Thanks for the responses.

                   

                I change the layout to have a 125 kHz clock going to a LUT.

                   

                A control Reg (1 bit) also went to LUT input (used as "ENABLE" signal)

                   

                The 2 output bits were control by LUT such that when ENABLE was "1", One output followed the Clock polarity while other was inverted.

                   

                This worked ok as far as signal generation but my FET drivers and Fets were getting warm (even with light load of 1K across bridge).

                   

                I have a reference design that is driven from a PIC controller that works fine and the only difference I can see is 1 machine cycle (250ns) delay between the pins being switched.

                   

                The drivers for the FETS are inverted (TC4426). I apply a "1" to one of the ICS (this switches the High side P FET ON and the low side N FET OFF on left side of bridge) and I apply "0" to inputs on other side that switched P FET OFF and N FET ON.

                   

                I wonder if there is small overlap and all are switching on for several hundre nanosecods and causing the heat?

                   

                If so, is there a way I can always ensure 1 output is switched before the other? ie. The "0" on one side applied before the "1" on the other. I suspect I need to discretely control each pin from software instead of using clock and LUT in this case?

                • 5. Re: Problem with Digital output timing
                  user_343349849

                   I took a look at some integrated solutions and found that ST produce a package that has a full bridge driver built into it with full protection. It also provides the required delay to prevent cross conduction when swithing. However, all of the models I found in the DMOS family (like the L6226) have upper switching frequency limit of 100kHz. 

                     

                  Can anyone recommend a suitable device that will go a bit higher in frequency ? (with 2.5A current capavility or more).

                     

                  This does work out economical as the one device replaces 4 ICs (the 2 drivers and 2 HEX FET ICs I am using at the moment)

                  • 6. Re: Problem with Digital output timing
                    user_14586677

                    Did you try -

                       

                     

                       

                    ON

                       

                    Infineon

                       

                    IRF

                       

                    Fairchild

                       

                    TI

                       

                     

                       

                    Many have selector and filtering tools such as

                       

                     

                       

                    www.onsemi.com/PowerSolutions/parametrics.do

                       

                     

                       

                    Regards, Dana.

                    • 7. Re: Problem with Digital output timing
                      user_343349849

                       It will take some tme to source alternate devices and lay up new PCB. In the meantime I would like to test my output circuit.

                         

                      Can anyone suggest a suitable method to achieve the following, the Pins need to be switched in order shown to avoid turning both FETS of a side of the bridge on at same time. I can get the switching sequence ok if I don't use hardware clock but have toruble gettings accurrate ON OFF times in code. (Or shoudl I disable interrupts during transmission and use NOP for delay and then reenable interrupts after? The CLOCK component works real well but I cannot figure out how to ensure port pins switch in sequence below as the cock state or enable function changes. Thanks

                         

                      125kHz clock (4us HIGH, 4us LOW).

                         

                      Clock goes HIGH

                         

                      PMOS2 = 0

                         

                      NMOS2 = 0

                         

                      NMOS1 = 1

                         

                      PMOS1 = 0

                         

                      Clock goes LOW

                         

                      PMOS1 = 0

                         

                      NMOS1 = 0

                         

                      NMOS2 = 1

                         

                      PMOS2 = 1

                         

                      ALL OFF

                         

                      PMOS1 = 0

                         

                      PMOS2 = 0

                         

                      NMOS1 = 0

                         

                      NMOS2 = 0

                      • 8. Re: Problem with Digital output timing
                        user_343349849

                         The strange thing is that if I do not enable the interrupts and attempt to toogle the pins, I cannot get them to toggle faster then 5us ON and 9.8us OFF. The datasheet mentions the pins operating faster than 1MHz in fast mode (I have set fast mode and push pull output). I am using the CY8CKIT

                           

                        Is this related to the "Write" API or is something else affecting the timing? Here is my simple code.

                           

                        #include <project.h>

                           

                        void LF_ONE(void)

                           

                        {

                           

                            PMOS2_Write(0);

                           

                            NMOS2_Write(0);

                           

                            NMOS1_Write(1);

                           

                            PMOS1_Write(1);

                           

                            asm("nop");

                           

                        }

                           

                        void LF_ZERO(void)

                           

                        {

                           

                            PMOS1_Write(0);

                           

                            NMOS1_Write(0);

                           

                            NMOS2_Write(1);

                           

                            PMOS2_Write(1);

                           

                            asm("nop");

                           

                        }

                           

                        void SendCarrierBurst(void)

                           

                        {

                           

                           LF_ONE();

                           

                           LF_ZERO();

                           

                        }

                           

                         

                           

                        int main()

                           

                        {

                           

                            PMOS1_Write(0);

                           

                            PMOS2_Write(0);

                           

                            NMOS1_Write(0);

                           

                            NMOS2_Write(0);

                           

                            for(;;)

                           

                            {

                           

                              SendCarrierBurst();

                           

                            }

                           

                        }

                        • 9. Re: Problem with Digital output timing
                          user_14586677

                          You have seen the discussion in this ap note about speeding

                             

                          up pin toggling rate ?

                             

                           

                             

                              

                             

                                    http://www.cypress.com/?rID=57571     AN72382 - Using PSoC® 3 and PSoC 5LP GPIO Pins

                             

                           

                             

                          Regtards, Dana.

                          • 10. Re: Problem with Digital output timing
                            user_343349849

                             Thanks for the info.

                               

                            I redid the code using the fast IO method and was able to get period below 2us now. 

                               

                            I disabled the interrupts, bit bashed the port bits (with nop'sto set exact required delay) and now it all works fine.