4 Replies Latest reply on Oct 8, 2013 8:46 PM by hiroyasu.koike

    Decoupling capacitor for CYF0018V

    hiroyasu.koike

      Is there any recommendation or example for decoupling capacitor on CYF0018V of

         

      Vcc1,  Vcc2 and  Vccio?

         

      I will apply 25MHz clock into WCLK and RCLK.

         

      Regards,

         

      Koike

        • 1. Re: Decoupling capacitor for CYF0018V
          sheetal.darshan

          Hi Koike,

             

              

             

                    PFA the "PCB Layout guidelines for HDFIFO CYF0018V.pdf"

             

          Please let us know if you need more information on the same.

             

          Thanks,

             

          Sheetal

          • 2. Re: Decoupling capacitor for CYF0018V
            hiroyasu.koike
                    Hi Sheetal, Thank you for quick replying. This helps me a lot. But let me ask a few more questions. >4)JTAG pins: >TMS/TRST -Point-to-Point connection with a pull-down resistor on the line.(R=?). TCK, >TDI, TDO should be point to point connections. I'm thinking killing the function of JTAG. How should I take care of JTAG input pins? >VCC2- connect to 1.5V. Special care has to be taken for this supply to ensue these >power pins are as noise free as possible. I understood "Special care has to be taken", but how should I design circuit, exactly? Some example would be appreciated. >Vref - Use 10uF and 0.1uF de-coupling capacitors. Place .1uF de-coupling close to the >pin. If common supply used, have a common 10uF and individual 0.1uF decoupling >capacitors I thought resistive devided circuit was good enough but now I'm wondering. Any recommendations for Vref? >6) Pin U6- DNU -Connect a weak pull down. Pulling down to Vss directly (or open) is not allowed? Regards, Koike   
            • 3. Re: Decoupling capacitor for CYF0018V
              hiroyasu.koike
                      Hi Sheetal, Let me resend mail. Thank you for quick replying. This helps me a lot. But let me ask a few more questions. >4)JTAG pins: >TMS/TRST -Point-to-Point connection with a pull-down resistor on the line.(R=?). TCK, >TDI, TDO should be point to point connections. I'm thinking killing the function of JTAG. How should I take care of JTAG input pins? >VCC2- connect to 1.5V. Special care has to be taken for this supply to ensue these >power pins are as noise free as possible. I understood "Special care has to be taken", but how should I design circuit, exactly? Some example would be appreciated. >Vref - Use 10uF and 0.1uF de-coupling capacitors. Place .1uF de-coupling close to the >pin. If common supply used, have a common 10uF and individual 0.1uF decoupling >capacitors I thought resistive devided circuit was good enough but now I'm wondering. Any recommendations for Vref? >6) Pin U6- DNU -Connect a weak pull down. Pulling down to Vss directly (or open) is not allowed? Regards, Koike   
              • 4. Re: Decoupling capacitor for CYF0018V
                sheetal.darshan

                Hi Koike,

                   

                We understand your concern & request you to create a Tech Support Case on Cypress Website. Else you can share your email ID & we will create a case on your behalf. Please share your design schematic on tech support case to help you with the solution at the earliest.

                   

                Thanks,

                   

                Sheetal

                • 5. Re: Decoupling capacitor for CYF0018V
                  hiroyasu.koike

                  I've got perfect answer from Tech Support, so I forward this mail for anyone in the future.

                     

                  Hi Koike-san,

                     

                  Greetings!

                     

                  Here are the answers to your questions:

                     

                  Question: JTAG pins: I'm thinking killing the function of JTAG. How should I take care of JTAG input pins?

                     

                  Solution: If you are not using the JTAG functionality, then the pins shall have the following:
                  1. TRST: Connect to GND through a Pull-Down resistance of 1Kohm to ensure the test access port is held in the reset mode.
                  2. TMS: Connect to GND
                  3. TDI: Connect to GND
                  4. TCK: Connect to GND
                  5. TDO: Can be left Floating

                     

                  Question: VCC2- connect to 1.5V. Special care has to be taken for this supply to ensue these power pins are as noise free as possible. I understood "Special care has to be taken", but how should I design circuit, exactly? Some example would be appreciated.

                     

                  Solution: Vcc2(1.5V), capacitor of 10uF bulk close to the voltage supply end and a .01uF de-coupling close to the device pin is to be placed. Since Vref is a biasing voltage generated from the Vcc2, hence there will be negligible current consumption and a decoupling capacitor of 0.1uF is required to be placed close to the device.

                     

                  Question: Vref - Use 10uF and 0.1uF de-coupling capacitors. Place .1uF de-coupling close to the pin. If common supply used, have a common 10uF and individual 0.1uF decoupling capacitors. I thought resistive divided circuit was good enough but now I'm wondering. Any recommendations for Vref?

                     

                  Solution: “If common supply used, have a common 10uF and individual 0.1uF decoupling capacitors”, we meant Vref is generated from Vcc2 using the resistive divider network, then 10uF bulk close to the Vcc2 voltage supply end & decoupling capacitor of 0.1uF close to the device for Vcc2 & Vref (since Vref is a biasing voltage generated from the Vcc2, there will be negligible current consumption & a decoupling capacitor of 0.1uF close to the device) to be placed.

                     

                  Question: Pin U6- DNU -Connect a weak pull down. Pulling down to Vss directly (or open) is not allowed?

                     

                  Solution: We are sorry. As per the datasheet, this pin should be tied to VSS preferably or can be left floating to ensure normal operation.

                     

                  Thanks for contacting Cypress Tech Support. Feel free to contact us if you have any further query on this.

                     

                  Regards,
                  Asha