5 Replies Latest reply on Dec 11, 2014 1:21 PM by user_14586677

    Power Cycle Programming

    user_185194099

      We are using a PSoC 3 in the 48-pin MQF (CY8C3866LTI-067) and we are so tight in pins that we could not use the hardware reset option, but had to declare P1[2] as GPIO. 

         

      So for re-programming we have two options - power cycle and bootloader (soldering pre-programmed devices to the board).

         

      Power cycle programming turned out to be difficult first, the reason was that we had too many decouple capacitors (>400 microfarad ceramic) on the board. After we reduced it, it works reliable -though Cypress seems not to recommend it.

         

      For bootloading with pre-programmed devices we had the difficulty that obviously the manufacturer had not programmed the NVLs, so the bootloader refused to re-program the flash.

         

      One question arises (for both PSoC 3 and PSoC 5LP which we use on other boards): 

         

      How can I read the non-volatile latches from the PSoC processor?

         

       

         

      Andreas

        • 1. Re: Power Cycle Programming
          user_1377889

          Andreas

             

          I would suggest you to file a MyCase and discuss that with Cypress directly. So they could probably help you. You may upload the programmed Hex-file to verify what should and what has been programmed.

             

          To do so, on top of this page "Support & Community -> Technical Support -> Create a MyCase" .

             

           

             

          Bob

          • 2. Re: Power Cycle Programming
            user_14586677

            The register map looks like below. So use register access define in system

               

            reference guide, Creator Documentation. Although reg writes also shown in

               

            guide I do not think taht is possible per TRM, see the section on NVL there

               

            for additional info. The one thing I thought was odd I compiled and empty PSOC

               

            3 project and no masks were defined for the register fields.......I searched the

               

            entire project.

               

             

               

            Register Access APIs
            uint8 CY_GET_REG8(uint16/uint32 reg)
            Description: Reads the 8-bit value from the specified register. For PSoC 3, the address must be
            in the lower 64 K address range.
            Parameters: reg: Register address (uint16 PSoC 3, uint32 PSoC 4/PSoC 5LP)
            Return Value: Read value


               

             

               

             

            • 3. Re: Power Cycle Programming
              pavankumar.vibhute

              Hi Andrea,
              Do you mean chip flash is in fully protected mode (NV latch settings making flash to fully protected including internal writes) ? I think it is not in fully protected mode. Have you tried writing an array of flash from main.c ?

              • 4. Re: Power Cycle Programming
                user_185194099

                @pvkv:

                   

                Sorry if I did not express it clearly enough: if you have a bootloader/bootloadable system,

                   

                in the moment that you try to program the device flash with the bootloader with a new application, 

                   

                the bootloader seems to check that the values in the NVL match.

                   

                The NVL control things like the reset state of I/O pins, whether the optional reset is used and which debugging options are enabled. When you build a project, PSoC Creator ensures that the NVL match between bootloader and bootloadable, but in my case I think the external service company which programmed our devices before soldering, did not program the NVL.

                   

                 

                   

                @bob/dana:

                   

                I followed your recommendation and opened an issue:

                   

                The NVL latches are not accessible as registers or memory mapped, but through the programming interface (Section 43 of the TRM). I overlooked this as I relied on the standard methods (microprog/bootloader) for programming.

                   

                The programming interface can be used to send a read-byte command to the NVL and thus get its content.

                   

                I did not find any standard libraries in PSoC Creator to do this, I will experiment with it and come back to the forum.

                   

                (But probably not this year).

                   

                Andreas

                • 5. Re: Power Cycle Programming
                  user_14586677

                  Power cycle programming turned out to be difficult first, the reason was that we had too many decouple capacitors (>400 microfarad ceramic) on the board. After we reduced it, it works reliable -though Cypress seems not to recommend it.

                     

                   

                     

                  For this problem you could always jumper a ground buss, not ideal, but

                     

                  if done right should work. This way you could meet all decoupling recommendations,

                     

                  which should be done.

                     

                   

                     

                  Otherwise look at board for noise using DSO on infinite persistence. To make

                     

                  sure there is not a problem area your reduced bypassing may cause you,

                     

                  especially later in the field.

                     

                   

                     

                  Regards, Dana.