Can you please provide us with an example showing your error? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
Thanks Bob, Dana. I will read thru that document again. I don't remember any info in there about one or multiple clock sources of the same frequency. Any thoughts there? Is it always better to use one clock source?
Attached is the timing report for an earlier version of a design I am doing for a client. As you can see, CyMASTER_CLK is negative.
Because my client does not want the design made public, I will try and produce a subset design that fails in the same way.
The current version of the design is down to one hold time violation of less than 0.4 ns and no frequency issues so I will probably go with that.
NegFreqDemo_timing.html.zip 28.6 K
You can always file a CASE directly and Cypress will treat
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