3 Replies Latest reply on Jan 6, 2015 9:20 AM by f..nouwt

    Slave FIFO Problems

    f..nouwt
              I am trying to use the slave FIFO example with a Super Speed Explorer Kit and a Spartan 6 FPGA (Papillio Pro). It works as expected, but there is one big problem: When doing IN transfers (setting the FPGA in IN Stream mode using the dipswitchs) fast after eachother (for example by using streamer.exe), the endpoint stalls. Only resetting the pipe will fix this issue. (but it occurs again if you do a lot of transfers). Writing to the USB works great, up to 300 MByte/s. But that's not what I need.   
        • 1. Re: Slave FIFO Problems
          shashank.rebbapragada

          How do you determine that the endpoint halts?

             

          Does this happen only on a specific PC? Which USB3 host controller does the PC have?

             

          We have not seen such an issue in our tests.

             

          Do you get a similar issue if you try streaming with UsbBulkSrcSink firmware?

          • 2. Re: Slave FIFO Problems
            f..nouwt

            How do you determine that the endpoint halts?

               

            The URB status reported by the Control Center shows it. Only resetting wil get it back working.

               

            Does this happen only on a specific PC? Which USB3 host controller does the PC have?

               

            I tested it on 2 pcs. One with an USB 2.0 Controller and one with an USB 3.0 Controller. The USB 3.0 one is an Intel 7 Series/C216 Chipset Family USB Enhanced Host Controller. The USB 2.0 is an Intel 5 Series/3400 Series Chipset Family USB Enhanced Host Controller.

               

            We have not seen such an issue in our tests.

               

            Do you get a similar issue if you try streaming with UsbBulkSrcSink firmware?

               

            With the firmware thats in my Super Speed Explorer Kit by default, I don't have this problem, so it must be somehow related to the slave fifo interface. Also, if I compile the firmware from source it does not work at all (I want to compile it because currently it's in 32 bit mode, but I have only connected 16 bit to my fpga). The precompiled ones work, but have the stalling problem.

            • 3. Re: Slave FIFO Problems
              f..nouwt
                      The problem seems to be related to the flags. If I remove the flag checks in the vhdl (aka. it just writes, also if the buffers are swapped), it works flawlessly. But of course, there is a data loss, because it still writes while the buffers are swapped. Any idea what the problem might be?