2 Replies Latest reply on Jan 8, 2015 11:27 PM by userc_38441

    Behaviour of UDB F0/F1 with single buffer FIFO





      in our project we are using a self developed core using some datapaths. FIFO is disabled through AUX registers (CLR bits are set) to minimze delay.




      Will the content of F0/F1 be overwritten with rising signal on f0/f1_load, even if the content wasn't read before? Again: FIFO is in single buffer (= register/latch?) mode.




      From my obersavtion I have to first read F0/F1, than the UDB can write a new actual value. Is this correct?