6 Replies Latest reply on Jan 20, 2015 4:42 PM by user_385660486

    About USB D+ D- voltage supply


      I am designing a small battery operated device that must operate without a USB connection, but at times connect to USB for both communication and battery charging.  I would like to use 2.5V for Vddd.  I am concerned about the signaling voltage levels on D+ and D-.  My research suggests that these need to have a 3V differential between them.  But how is this possible when Vddd is only 2.5V?  I don't see facility anywhere to use the 5V VBUS for *strictly* USB purposes, because D+ and D- pins are specially designed to use Vddd and not a Vddio pin.


      Meanwhile, in the PSoC5 LP datasheet I find on page 73 table 11-14, cases quoting Vddd=1.8V.  This implies the task can be done with Vddd=2.5V.  But how is Vohusb in the same table produced to be between 2.8V and 3.6V?  I have seen mention of a 3.3V regulator, but if that's the solution, I would worry that it's only a step-down regulator without step-up capability from 1.8V or 2.5V up to 3.3V.


      I've been searching for a while for an appnote or other advice on how to do PSoC5 LP usb communication with Vddd below 3V, such as my desired 2.5V or the previously table implied 1.8V.  But I can't find anything.


      Is there advice out there somewhere?  Or can you please offer advice?  Is there a simple solution here?


      It does occur to me to make Vddd automagically float up from 2.5V (battery power) to 3.3V (when USB connected), and then use a separate Vddio=2.5V pin for interfacing with my 2.5V-only peripheral.  Perhaps involve an ideal-diode chip.  But this gets a little complicated.  I'd rather not have to do that if there is a more simple solution.


      Finally, I would also like for my software to know when the USB is connected.  For this purpose, I am considering using the VBUS to GPIO circuit on page 16 of the USBFS_v2_50.pdf datasheet.  I realize this uses the resistor divider to reduce 5V to 3.3V, so I would use two 30K resistors to reduce 5V to 2.5V.  Yes, I know this is simple and understand it.  I came to this point, however, by considering configuring the USBFS component to do "Enable VBUS Monitoring".  I believe that's intended for self-powered devices.  Maybe I should just use it as GPIO and be done with it,  But the whole "Enable VBUS Monitoring" and self-powered vs bus-powered question sort of bleeds over into this subject as well.


      Thanks very much in advance for your help.



        • 1. Re: About USB D+ D- voltage supply

          I saw this on a site (note required differential at receiver)  -









          Unless you are designing the silicon for a USB device/transceiver or USB host/hub, there is not all that much you need to know about the electrical specifications in chapter 7. We briefly address the essential points here.


          As we have discussed, USB uses a differential transmission pair for data. This is encoded using NRZI and is bit stuffed to ensure adequate transitions in the data stream. On low and full speed devices, a differential ‘1’ is transmitted by pulling D+ over 2.8V with a 15K ohm resistor pulled to ground and D- under 0.3V with a 1.5K ohm resistor pulled to 3.6V. A differential ‘0’ on the other hand is a D- greater than 2.8V and a D+ less than 0.3V with the same appropriate pull down/up resistors.


          The receiver defines a differential ‘1’ as D+ 200mV greater than D- and a differential ‘0’ as D+ 200mV less than D-. The polarity of the signal is inverted depending on the speed of the bus. Therefore the terms ‘J’ and ‘K’ states are used in signifying the logic levels. In low speed a ‘J’ state is a differential 0. In high speed a ‘J’ state is a differential 1.


          USB transceivers will have both differential and single ended outputs. Certain bus states are indicated by single ended signals on D+, D- or both. For example a single ended zero or SE0 can be used to signify a device reset if held for more than 10mS. A SE0 is generated by holding both D- and D+ low (< 0.3V). Single ended and differential outputs are important to note if you are using a transceiver and FPGA as your USB device. You cannot get away with sampling just the differential output.


          The low speed/full speed bus has a characteristic impedance of 90 ohms +/- 15%. It is therefore important to observe the datasheet when selecting impedance matching series resistors for D+ and D-. Any good datasheet should specify these values and tolerances.


          High Speed (480Mbits/s) mode uses a 17.78mA constant current for signalling to reduce noise.










          Regards, Dana.

          • 2. Re: About USB D+ D- voltage supply

            Detecting USB connection -










            Regards, Dana.

            • 3. Re: About USB D+ D- voltage supply



              Thanks very much for the auxilliary information.  I'll look it over.  Unfortunately, it does *not* address my primary question.


              Do you happen to know more about the actual voltage production capability of the PSoC5LP?  I'm concerned about a gap in the documentation.  None of the Cypress doc shows lower Vddd levels in use.  It's very, very possible that the USB does not work whenever Vddd is below 3V.  This would be exactly the kind of documentation gap to cost me a lot of money, finding out only after designing and paying for a prototype pcb to be manufactured.  I believe the PSoC has a Boost regulator, but Buck/Boost regulators are uncommon.  So it's very possible that the PSoC doesn't have one.  And if it doesn't, then how can it possibly produce the required voltage differential when Vddd is below 3V?  Yes, there's a Boost regulator associated with VBOOST and nearby pins, and that can be used to convert a lower voltage to a higher one to subsequently provide to Vddd.  But nowhere in the doc does it say this is necessary for USB D+ D- to work, if otherwise Vddd is below 3V.  I assume there's not another a hidden, undocumented boost regulator just for USB?  And I hope it's not expecting to work with differentials as low as the 1.71V minimum Vddd...


              Thanks again,



              • 4. Re: About USB D+ D- voltage supply

                 My parallel MyCase was answered, with USB won't work for Vddd less than 2.85V.  The info appears in the USBFS_V2_50.pdf, but it's very poorly described.  I had seen this before, but since it was so poorly described. I was uncertain.

                • 5. Re: About USB D+ D- voltage supply

                  Did they explain why in light of the small differential needed by USB ?


                  Seems to me if I/O will operate a P-P totem pole output that a couple


                  hundred mV of needed differential should be possible.




                  Glad you got your answer as I was about to suggest posting a CASE.




                  Regards, Dana.

                  • 6. Re: About USB D+ D- voltage supply

                    I Never use it but there is an integrated Boost converter in the psoc 5lp requiring external components to boost the voltage and filter noises and peaks. For these purposes you need an inductor, a capacitor and a diode, there is a reference design in the following application note. Reading the psoc datasheet, you can boost vbat to 3.3v (vddd&vdda) to make the usb subsystem to work properly with an efficiency of 83%. The rest of vddios could be powered using vbat...