By the way, the invertors shown on external circuit are actually part of the MOSFET driver IC's and the MOSFETS are matched pairs in IC's, the invertors are shown to explain switching logic levels
Can you guarantee that under all circumstances as power-up, initialization, reset and power down the PSoC outputs can not cause a shortcut in your bridge?
An H Bridge datasheet shows worst case Ton, Toff delays under T, V conditions.
If it does not don't use it, it is incompletely characterized.
So those numbers + some margin designer feels comfortable with to cover layout
and any other issues become dead band settings. Many H bridge offerings even
include Safe Area, Thermal, and the actual timing circuits, so even dead band is
irrelevant from external PWM.
i am trying too using PSOC 5 to produce two phase shift signals with dead band. I notice that you have the same problem. Could you help me if you had found the solution for this issue?
Just look at global properties and setup -