To clarify a bit, I've tried using DelSigPlus once and ADCINC the other time, both had the same symptoms. I've also tried 12bit with similar results.
Post an archive of your project so we can see all settings -
The first thing I see are you have read modify writes to ports with
mixed I/O. You need to use shadow registers, see ap note for discussion.
http://www.cypress.com/?rID=2900 AN2094 - PSoC® 1 - Getting Started with GPIO
Keep in mind this constraint, from PGA datasheet -
The input and output voltage ranges of the amplifier do not extend to the power supplies (i.e., they are not "rail-to-rail" opamps). The allowed input range is a combination of input limit, output limit, power supply voltage, analog ground value, and selected gain. This is illustrated in the DC and AC Electrical Characteristics section.
You can eliminate the PGA and its CM problems, as well as its offsets, drift,
by connecting + ADCinc input directly to a pin. P2_1 in this case. Otherwise
set OpAmp bias in global properties to high power.
You have the column clock for ADCinc set at 1 Mhz, but optimal from datasheet
is 2 Mhz.
Your CPU clk is set for Sysclk/8, unless you are trying to save power consider
setting it to Sysclk/1.
If the INA125 is running off split supplies keep in mind the CM input range for
PSOC 1 is analog ground / Vss, you cannot input - signals into PSOC. So you
have to offset the INA125 output.
I just tried the opamp high power option and the clock changes recommendations. The sensitivity is better, but still not enough. I'm going to try switching out the PGA and give the other option you suggested a try.
I changed to read P2_1 and got rid of PGA. Unfortunaly same results. I added weights until the ADC reported a +1 division change and that was a difference of 69mV. For lack of better describing terms, the resolution I got from this simple incomplete test is that I'm getting 69mV/div instead of the calculated .3mV/div for the 14bit ADC.
I think there's still some setting I'm getting wrong...
Thank you for your continued help.
Your reference is Vdd, a divider off that. Point is are you averaging readings
to take out noise ? A good measure is to use your DSO on infinite persistence
and look at Vdd rail. You will probably see at least a couple hundred mV which
you need to reduce.
Best bulk caps for this purpose is Polymer Tantalum, their ESR curves and order
of magnitude better than traditional Tanatalums, And of course a ceramic disk in
parallel. 01 uF or better.
Do you have a link for the load cell datasheet ?
I will look to improve VCC noise.
I haven't been averaging or doing any filtering. I'm actually hoping to see the noise in the ADC reading, but do not see any. The readings are consistently one value until I try to apply at least 69mV worth of weight, in which case it goes up, but once I remove the weight, the ADC goes back to the initial value. Can't see any noise in the ADC readings.
Load Cell: SBO-2K (https://www.transducertechniques.com/sbo-load-cell.aspx)
I improved the VCC a bit, but maybe is not there yet. I have the VCC ripple down to 60mV peak to peak. I'll look into getting a quieter supply.
Another bit of information about what I just observed. This is rough estimates and not precisely measured at all.
Placing 30lbs on the LC, the ADC reports a +1 change, placing 31lbs has a +2 change, 32lbs, gives +3 change...
Thank you for your help.
First a lkittle troublshooting -
1) Connect ADCinc input to a pot connected to VDD. Using a voltmeter
set the pot to different positions and compare what you read on voltmeter to
what PSOC is producing.
Remember ADCINC_iClearFlagGetData() returns a signed integer, Vdd/2 input =
Would it still return a signed integer when the setting has been changed to unsigned in the configuration GUI?
Looking at .lst file the ASM does not appear to test for global
flag/setting, however I am not an ASM program capable person
on this processor. The pot test should quickly answer that question.
I put a 10k pot and checked the ranges and they seem to behave like they should. Changing the pot to yield 18mV change gave the ADC a change of 2 division. The math doesn't seem to be correct, but this might be because the signed /unsigned setting is not correct.
ADC count of 0x1243 for 583mV reading on the oscope. Mathematically 0x1243 should yield 4675*(5/(2^14))= 1.426V but that might be something else I can deal with after calibration and filtering.
The symptoms seems very strange though, with the pot the ADC values seem to change linearly with change in voltages, however with the INA125 output it does not seem to be that way.
Mathematically 0x1243 should yield 4675*(5/(2^14))= 1.426V
If its signed then it would be 4675*(2.5/2^13) + 2.5 = 3.93 V
Don't forget to pay attention to the Common Mode Range limitations
of the IA125, from datasheet -
INPUT COMMON-MODE RANGE
The input common-mode range of the INA125 is shown in
the typical performance curves. The common-mode range is
limited on the negative side by the output voltage swing of
A2, an internal circuit node that cannot be measured on an
external pin. The output voltage of A2 can be expressed as:
V02 = 1.3VIN – (VIN – VIN) (10kΩ/RG)
(voltages referred to IAREF terminal, pin 5)
The internal op amp A2 is identical to A1. Its output swing
is limited to approximately 0.8V from the positive supply
and 0.25V from the negative supply. When the input com
mon-mode range is exceeded (A2’s output is saturated), A1
can still be in linear operation, responding to changes in the
non-inverting input voltage. The output voltage, however,
will be invalid.