We don’t have any differential receiver in the SRAM. We have all the comparators at the input of the SRAM which compares the input with Vref. If the SRAM has ODT feature on K and /K inputs, we can also enable the On-Chip Termination Resistor on these pins and you can route the signals as single ended.
You write that CQ/CQ# and K/K# are not truly differential signals. Must these traces be routed to have 50-Ω impedance and should be kept away from each other (for example CQ from CQ# and K from K#) to a minimum of 5x the trace width (AN4065)?
Does this ruling of pseudo differential clocks for K/K# or CQ/CQ# hold true even for QDR-II+ Extreme ?
I have CY7C2565XV18 daughter cards and I am using single pin of rx clock i.e. CQ as reference clock to generate phase shifts 90deg in clock internally to align to incoming data Q in my FPGA design. Is this correct way ?
Thanks & Regards,