3 Replies Latest reply on Jan 27, 2015 3:38 AM by noskov.sergey

    Should the Clocks in QDR/DDR Sync SRAMs be routed as Single Ended or Differential?

              Echo clocks (CQ and /CQ) are not truly differential signals. They are single ended signals which are 180 degrees out of phase .So, we need to route these signals as single ended but we need to ensure that, both should have minimum skew with respect to each other. K and /K clocks are also not truly differential clock signals. Please note that there is no differential receiver in the SRAM. The memory uses the rising edges of K and /K to latch input signals. Both clocks are single ended signals. Although they are not truly differential, it is advised to keep K and /K 180 degrees out of phase with respect to one another. Also please note that there is no special requirement to route CQ and /CQ and K and /K close to each other, however trace characteristic, length should match so that there is no skew between them. Since in this case it is pseudo differential clocks, rising edge of one clock and falling edge of the other clock should match and there should not be any skew between them.