2 Replies Latest reply on Jan 28, 2015 9:24 AM by noskov.sergey

    Decoupling Capacitor Recommendations for Power Supply Pins while designing QDR/DDR SRAMs


       We have a reference design schematic for QDR/DDR SRAMs that is provided in the follwoing link:http://www.cypress.com/?id=4&rID=72249.


      The decoupling capacitors that can be used in the design has also been shown in the schematic. Following are few points regarding this:


      1. The lower value capacitors (0.01 and 0.1 uF) are meant for decoupling. 10 uF forms the bulk capacitor and 2.2 uF capacitors are the bypass capacitors.There are basically few differences between Decoupling and Bypass capacitors. Decoupling Capacitors (which are of low values ) would basically filter the Power Supply so that any noise or random fluctuations in the power-supply is filtered. Bypass capacitors (which are of comparatively higher value) would store electrical charge that is released to the power line whenever a transient voltage spike occurs. For example, these capacitors would provide the necessary current in case of voltage transients (Low-High or High-Low) while driving the I/Os.


      2. The decoupling and by-pass capacitors supply current for "instant" demands. The larger the current, the more value you will need. If 2 chips are used, then we recommend to use each set near the chips. Also please note that if width increases, then the total current taken from the supply will vary and shall increase the requirements for more capacitors to ensure that the target impedance is met. Otherwise there are chances that a spike will be seen when large currents are drawn due to switching noise.


      Also please note that the location of placement is important, and should be close to where it is actually needed. 
      It is best to run simulation to ensure that the placement is effective. This is the best input that can be given.




      PSoC Wonders