The delay you see is the buffer switching delay. It cannot be avoided even with a low level implementation since this is a hardware limitation.
Your best bet is to implement option 2.
You cannot use DMA_RDY_THx in the transition equation and then use a DR_DATA or IN_DATA action for a thread other than 'x' in the end state. This is again a limitation with the internal GPIFII architecture.
This is the reason we use a counter in the state machine of An75779.
You can try to do the same. Setup a counter such that it hits at the buffer boundary and switch to the next state when the counter hits. In the next state, you would drive data from another thread1 instead of thread0. And vice versa.
Of course, this implementation assumes that you always have data available in both threads all the time.
If it is absolutely neccesary that you check for data availability before performing DR_DATA, you would need to implement an intermediary dummy state between the two DR_DATA states for the two threads.
Thank you so much for the reply.
I am now trying to implement option 2 as you suggested (using two counters), but I have problem with GPIF when connecting two linked states with DR_DATA from different thread. Please see the attached image for the error message.
Can you please verify this is another limitation of the GPIF? Or do you think there is another way to achieve the transition other than using the "GPIF II Designer"? Thanks
I think by successfully doing this, I can avoid using another FPGA to regulate the output timing. Thanks again.
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I forgot about this limitation with DR_DATA. It is a GPIF limitation unfortunately. It does not exist for IN_DATA. And it cannot be worked around.
Apologize for my mistake.
Your only option to achieve this is to use intermediary states like shown in the attached screenshot.
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Thank you. That clarifies a lot for me. I will use another FGPA to regulate timing. Thanks again.