There are several possibilities.
A basic method is to feed a sample set of test voltages to the PGA, capture
the difference, and do a least squares curve error fit or a power curve fit,
that yields equation coefficients, and future readings are then processed by that
errror correcting equation.
This can be done via GPIB or VMx test instrumnetation during manufacturing test.
A simple cal routine where PSOC controls the forcing generator and performs the
test readings/curve fit.
Or you could do a simple interpolation scheme. Again a test sample set measured,
and the resulting sample set used to interprolate values measured.
possible reason is that PGA input impedance varies with gain, becoming as low as ~20k range at high G (see the datasheet). So, PGA impedance becomes comparable with e.g. thermistor circuit impedance (e.g. ~10k). Here error comes. Note that Inverting/non inverting PGA have different impedances also.
My guess is that Hazique no longer looking at a 6 month old thread.
The lowest Zin is ~ 10K. The G error is a f() of Zin, onchip R error,
mux Rdson.... Onchip R error is quite significant, + 35%, - 25%, see
TIA conversion R specs.