8 Replies Latest reply on Feb 6, 2015 9:18 PM by user_6153427

    dma problem

    user_6153427

      I am repeatedly transmitting an array in sram over uart. It seems to work fine except that when I try to update the array with cpu access I am only able to intermittently get bytes into the array. Is there any type of blocking that can take place if dma is constantly reading from an array? I was under the impression that dma access to sram was clocked in such a way as to be transparent to cpu access. Has anyone else had a similar experience?

        • 1. Re: dma problem
          user_1377889

          Yopur assuptions are correct, DMA access happens "in between" CPU accesses without interfering each other. To check for your issue we need some more information: Can you post your complete project, so that we all can have a look at all of your settings? To do so, use
          Creator->File->Create Workspace Bundle (minimal)
          and attach the resulting file.



          Bob
           

          • 2. Re: dma problem
            user_6153427

            I think there must be something else going on here then. Here is my dma setup. It triggers from the Uart interrupt line on fifo empty.

               

             

               

             

               

            //init the dmx dma, 1 byte per burst, needs request for each burst, sram to uart,

               

             

               

            dmx1_dma_chnl_hndl = DMX1_DMA_DmaInitialize(1,1,HI16(CYDEV_SRAM_BASE),HI16(CYDEV_PERIPH_BASE));

               

            //allocate a td

               

            TD_Handle = CyDmaTdAllocate();

               

             

               

            //513 bytes of sram to transfer, disable after 513 bytes, enable the nrq, inc source address

            CyDmaTdSetConfiguration(TD_Handle,513,DMA_DISABLE_TD,(DMX1_DMA__TD_TERMOUT_EN | CY_DMA_TD_INC_SRC_ADR));

               
            //source and destination addresses

                CyDmaTdSetAddress(TD_Handle,LO16((uint32)dmx_out1),LO16((uint32)DMX1_UART_TXDATA_PTR));   

            //attach td to channel

               

             

               

            CyDmaChSetInitialTd(dmx1_dma_chnl_hndl,TD_Handle);

               

             

               

            And I call this to enable it and also restart it after sending 513 bytes.

               

             

               

            CyDmaChEnable(dmx1_dma_chnl_hndl,1);    //enable the uart dma

               
            • 3. Re: dma problem
              user_1377889

              As I said before, can you upload the COMPLETE project, please?

                 

               

                 

              Bob

              • 4. Re: dma problem
                user_302397898

                 This is an old posting but I will add comments for future searches in the forum.
                Two comments:  First; check this document http://www.cypress.com/?docID=44514 pages 5-6 which indicates that for most efficient performance, the transfer length in bytes should be an even multiple of spoke width (16 for DMA).  In your case, try 512 or 544 bytes.
                Second:  Open the memory map file (.map in the Results tab) and see if your arrays are loaded into high SRAM somewhere around 1FFFxxxx.  If you don't find them then you probably need to move your arrays into the global variables outside of main{}.
                As Bob Marlowe, said, posing your zip file from File >> Create Workspace Bundle would help the forum see what you are seeing.  You can strip it down to the minimum project necessary to demonstrate the problem.

                • 5. Re: dma problem
                  user_6153427

                  I had given up on this due to time and switched to using interrupts instead which work fine but require cpu time. I'll look into those suggestions to see if I can get it working better, thanks.

                  • 6. Re: dma problem
                    user_6153427
                            It appears from that document that the alignment is not so much an issue for byte transfers. I'm wondering if my problem might be from using the tx complete to trigger the dma. That uses a sticky bit and I'm not sure how you would clear it using dma. From an interrupt routine you read the status register to clear it.   
                    • 7. Re: dma problem
                      user_14586677

                      From a prior post in thread -

                         

                       

                         

                      DMA access happens "in between" CPU accesses without interfering each other.

                         

                       

                         

                      Thats not accurate, from TRM -

                         

                       

                         

                       

                      • 8. Re: dma problem
                        user_6153427
                                Well, I finally have it working on a psoc 3 but it's probably not that much different for the psoc 5. I'm triggering the transfer from sram to uart from the fifo empty tx interrupt. I'm transferring 512 bytes with one byte per burst. A sample project from Cypress using dma and a uart would be very helpful.