When you look at the CY8C38 family data sheet, you can find the pinouts for the different packages. From there you can see that only the 68 and 100 pin packages have 4 dedicated IDAC output pins.
The datasheet says the dedicated pins "should" be used on high current
range. I would posit this is because of a compliance range issue keeping
the IDAC in constant I mode. What you could do is using the analog view,
ohmeter, look at a route to a low R path and try it again to a "normal" GPIO
and get an idea of difference in path.
Note Rdson onchip of a mux, path, has wide variation, and no specs to guide
you on this. My point would be that if your "load" is anything but a virtual ground
a less desired route would have significant impact on compliance in addition
to inherent IDAC architecture contribution.
You could do some trial testing/testbed on compliance issue to see how much
margin there is before IDAC is pulled out of compliance
Just a thought.