8 Replies Latest reply on Aug 18, 2017 3:32 PM by piotr.borowy

    Use memory in Verilog component.






      I'm trying (for now) write easy verilog components for my Master Science thesis, and while making short LIFO stack I have problem, because: "Build error: memory declaration is not supported"


      Is there anyway to avoid this problem, for example, can you use somehow RAM build in PSoC 5LP, to make this component possible?