DSI Routing Interface

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Anonymous
Not applicable

Dear developer community,
In my recent project I investigate the performance of the PSocs. And now I have some questions to the DSI Routung Interface. Are there any performance data for the DSI for exampel the maximum frequency? And which delays are caused from the DSI? Does PSoC Creator calculate this delays?

Thank you for your effort
Raphael Löffler
 

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ETRO_SSN583
Level 9
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If you look at the results tab, workspace explorer, after a build,

   

there is a file projectname_timing.html that will show you

   

some timing info.

   

 

   

Regards, Dana.

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Anonymous
Not applicable

Thank you a lot for your answer. But I did not found there the spiecial delay from the DSI. And are there any performance data?

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ETRO_SSN583
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This might be useful (see the STA section) -

   

 

   

www.google.com/url

   

 

   

Regards, Dana.

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ETRO_SSN583
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This is a simple example (remember to click on lines to expand detail) -

   

 

   

 

   

Static Timing Analysis

                                                                                                                                                                                                       
Project :Design93
Build Time :02/24/15 08:29:57
Device :CY8C4245AXI-483
Temperature :-40C - 85C
VDDA :3.30
VDDD :3.30
Voltage :3.3
   
     Expand All |     Collapse All |     Show All Paths |     Hide All Paths   
   
    
      - Timing Violation Section     
    
     
      No Timing Violations     
    
   
   
    
      - Clock Summary Section     
    
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 
ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
CyHFCLKCyHFCLK24.000 MHz24.000 MHzN/A 
CyILOCyILO32.000 kHz32.000 kHzN/A 
CyIMOCyIMO24.000 MHz24.000 MHzN/A 
CyLFCLKCyLFCLK32.000 kHz32.000 kHzN/A 
CyRouted1CyRouted124.000 MHz24.000 MHzN/A 
CySYSCLKCySYSCLK24.000 MHz24.000 MHzN/A 
    
   
   
    
      - Clock To Output Section     
    
     
      
        - CyHFCLK       
      
                                                                                                                                                                                            
SourceDestinationDelay (ns)
cydff_1/qPin_1(0)_PAD22.463
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         
TypeLocationFanoutInstance/NetSourceDestDelay (ns)
macrocell1U(1,0)1cydff_1cydff_1/clock_0cydff_1/q1.250
Route 1cydff_1cydff_1/qPin_1(0)/pin_input5.683
iocell1P0[0]1Pin_1(0)Pin_1(0)/pin_inputPin_1(0)/pad_out15.530
Route 1Pin_1(0)_PADPin_1(0)/pad_outPin_1(0)_PAD0.000
Clock    Clock path delay0.000
      
     
    
   
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