1) SLCS# should be low during EPSWITCH# assertion. You can confirm this in the state machine of 5 Bit SlaveFifo Interface available in "Cypress Supplied Interface" section in GPIF II Designer tool
2) For the timing upto which EPSWICTH is asserted, please refer the following KB
We are sorry for the confusion caused by the documents. These will be updated soon.
- Madhu Sudhan
I am also confused but when I follow the link in (2) it tells me I am not authorized to access the page.
I'm currently considering to move from 2bit to 5bit slave fifo, and have exactly the same question as your 2nd one regarding the timeout.
Since you posted this a year ago, I was hoping you figured this out by now and perhaps you could explain how you figured the whole EPSWITCH to FLAG relation is?