6 Replies Latest reply on Feb 26, 2015 10:54 AM by user_14586677

    PSoC5LP DelSig problem with input range +/-Vref/4, /8, /16

    user_334126195

      Hi,

         

      I am trying to use Delta Sigma ADC with 16bit resolution in differential mode. I created 4 configurations, which differ only in input range (image for CFG0):

         
            
      • CFG0 - +/-1.024V
      •     
      • CFG1 - +/-0.256V
      •     
      • CFG2 - +/-0.128V
      •     
      • CFG3 - +/-0.064V
      •    
         

      I am using 10 Ohm resistor as a shunt to measure current going through a 10kOhm resistor at 3.3V. In topdesign I just connected two analog input pins to inputs of ADC.

         

      If I use configuration 0 (input range +/-1.024V), I get values that are similar to those that I measure with my multimeter, around 3.15mV. However, if I use any of the other 3 configurations, measured voltage is around 1.75mV.

         

      I have also tried to modify the CFG0 to use different input ranges, but I get same results. Also, if I use input range +/-0.512V, I get expected results (~3.15mV). So the problem appears when I use input range +/-0.256V, +/-0.128V and +/-0.064V.

         

       

         

      Am I doing something wrong? Are there any additional settings that need to be configured?

         

      Thanks!

         

      Strahinja

        • 1. Re: PSoC5LP DelSig problem with input range +/-Vref/4, /8, /16
          user_14586677

          I think you want to bypass your buffer as it does not allow

             

          the CM range you need. You need very close to rail capability,

             

          Vssa if 10 ohm in cold leg, Vdda if 10 ohm in hot leg.

             

           

             

           

          • 2. Re: PSoC5LP DelSig problem with input range +/-Vref/4, /8, /16
            Mark Hastings

            Straxy1,

               

            What is your common mode voltage?  If it is near Vss, you have two options, you can either use the level shift mode with the input buffer or use buffer bypass mode.  Since your source is a 10 ohm resistor, the lower input impedance of the ADC will not be a problem.  If you are doing high-side current measurement, and your common mode is near Vdda, bypass buffer mode is your only option.  Also with your common mode near Vdda, you won't be able to use an ADC gain above 2, meaning input range of +/- 1.024V (ADC gain = 1), or +/- 0.512V (ADC gain = 2).  Anything higher like +/- 0.256 (ADC gain = 4) will not work properly with a resolution of 16 bits or higher.  Although, if you drop down to a resolution of 15 bits you should be able to go all the was to an ADC gain of 16 (+/- 0.054V).

               

            Mark

            • 3. Re: PSoC5LP DelSig problem with input range +/-Vref/4, /8, /16
              user_14586677

              @meh, "Anything higher like +/- 0.256 (ADC gain = 4) will not work properly with a resolution of 16 bits or higher."

                 

               

                 

              Why wont the converter work at 16 bits, just not be capable of its total dynamic range due to 100 mV

                 

              limitiation above Vdd for CM range. I do not understand what is happening here. Seems to me the

                 

              converter should work for    Vdd + 100 mV >= Vx >= Vdd  - 0.256, bypass buffer mode.

                 

               

                 

              In posters case if he is using cold leg sense then his Vx never exceeds (3.3 x 10 ) / ( 10000 + 10 )

                 

              ~= 3.3 mV. In high side case ( 3.3 x 10000 ) / (10010 + 10 ) ~= 3.29 V.

                 

               

                 

              Regards, Dana.

              • 4. Re: PSoC5LP DelSig problem with input range +/-Vref/4, /8, /16
                user_334126195

                Just a bit more detail; Vdda in my design is 5V, and common mode voltage is ~3.3V (I am using external OpAmp to make sure voltage on 10kOhm resistor is ~3.3V). My 10Ohm resistor is on the high side.

                   

                 

                   

                 @meh: "Also with your common mode near Vdda, you won't be able to use an ADC gain above 2, meaning input range of +/- 1.024V (ADC gain = 1), or +/- 0.512V (ADC gain = 2).  Anything higher like +/- 0.256 (ADC gain = 4) will not work properly with a resolution of 16 bits or higher.  Although, if you drop down to a resolution of 15 bits you should be able to go all the was to an ADC gain of 16 (+/- 0.054V)."

                   

                 

                   

                Thank you for the suggestion, dropping resolution to 15 bits solved the problem!

                   

                I would like to ask if you can point me to documentation where this limitation of ADC is explained. Thanks!

                   

                Strahinja

                • 5. Re: PSoC5LP DelSig problem with input range +/-Vref/4, /8, /16
                  Mark Hastings

                  Dana,

                     

                  This ADC gain issue is only for ADC gains of 4 or larger (+/-0.256, +/- 0.128,  +/- 0.064) with a resolution of 16 bits or more and a common mode voltage above about 2 volts.  It has to do with how the larger input capacitor values are switched.  When the common mode voltage is above 2 volts the larger input caps used for the higher ADC gains will not be fully switched on. 

                     

                  Sorry for the confussion, but this problem was just recently confirmed and the ADC datasheet will be updated to reflect this issue.

                     

                   

                     

                  Mark

                  • 6. Re: PSoC5LP DelSig problem with input range +/-Vref/4, /8, /16
                    user_14586677

                    Thanks meh, I thought I was losing my marbles, which I am, just

                       

                    desire not to advertise it too often.

                       

                     

                       

                    Regards, Dana.