Going by the SPI master example program that available for the TCPWM SPI master components, the way to go is reading the interrupt flags and checking for the one that signals that the transfer is done. Just look into its code.
Thank you. I can absolutely look at the interrupt flag to determine when the shift register is complete, but it doesn't address the "race" between the transmitter shift register emptying (with the interrupt flag being set) and the SCB component negating SS# automatically because the shift register is empty and the transmit FIFO is empty. Is there any documentation on the specific timings involved there? The PSoC4 Architecture TRM goes into detail about SS# with some transfer modes but does not have the fantastic timing diagrams showing internal states and specifically WHEN SS# is negated.
When I look at the component data sheet, there is a diagram outlining how the SELECT lines are handled. (Page 104, 'SELECT and SCLK Timing Correlation')
Which datasheet are you referring to?
The PSoC4 SCB PSoC Creator component datasheet (v1.0) doesn't have 104 pages, nor does the PSoC 4200 general datasheet. The PSoC 4100/4200 Family TRM (registers TRM) doesn't have this information and the document I believe you're referring to (the PSoC 4100/4200 Family Architecture TRM) does not show any defined timing between the end of the shift operation, the "fifo empty" flag and the slave select. (indeed I can't find the word "correlation" in the document where it refers to anything SPI) and page 104 doesn't have anything relating to SPI Master mode.
I certainly appreciate any help you could offer. Which document are you seeing this in? Do you have a link to the specific document? I've checked the documents above and made sure that I was using the most recent versions available on the web site.
Hello, I got a similar Display working by connecting the D/C wire to a separate pin. and before i make the Write i set it correct to the value needed and after the write i set it back. even with mixing data an command bytes it works well.
@lexarion: interesting. I don't like the possible race condition which is why I was trying to avoid it, but as long as the D/C# line is in the correct state when the last bit is shifted out it should work, as you mentioned. Thank you for sharing your experience.
I ended up using a ST7565-based LCD display as I had damaged my SSD1322 OLED display some time previous (unrelated to SPI transfers) -- the ST7565 also has a D/C# line but it's used differently and thus doesn't have this issue.
@hli: I'm using PSoC Creator 3.0SP2. I haven't updated to 3.1 yet as I don't want to risk breaking things from updating the components.
I looked at the document you linked but it still does not give me accurate timing information about when the slave select will be negated after the byte has been shifted out of the shift register and there are no more bytes in the outgoing FIFO.
Compare the almost-useless timing information in the PSoC4 SCB datasheet with the very useful timing information given on page 26 of hte SPI Master v2.40 datasheet (http://www.cypress.com/?docID=43166).
The document I linked tells on page 104 that SELECT is de-asserted 1/2 SCLK period after the last SCLK period (when CPHA=0, it 1 SCLK period when CPHA=1). The times are 1/4 SCLK period shorter on the BLE devices.
Right, I understand but again this is insufficient data. I'm not blaming you but I am trying to point out why it is insufficient.
I understand that SS will be negatied 1/2 SCK (CPHA=0, PSoC4) after the last bit is transmitted, as per the diagram on page 105. It doesn't give any indication of the following timing relations:
- From "transmitter empty" flag being set to SS# being negated
- From "TX FIFO Empty" flag being set to beginning of transmitter shift operation
Now... I can make some assumptions (from tx empty to SS# negation is what the diagram is showing) but I'd imagine that this information is documented somewhere internally and is deterministic, which is why a nice graphic showing SCK, SS# and the various points at which things happen would be useful.
I think the biggest issue isn't the fact that I can't precisely tell when a character has been fully transmitted but more that I have no way of *ensuring* SS# is held active while I wait for the transmitter to empty so I can control another line (D/C# in the OLED example) at precise times.
Anyway -- I think we've got to a conclusion. It's just a pity it isn't the one I was hoping for. :-) Thank you once again for all of your assistance. It's very much appreciated.
- SPI DONE is set when the last element has been transmitted (page 85)
- SS# will be de-asserted 1/2 to 1 clock cylce later
- at this moment the last data element has been received (read is delayed from write)
- TX FIFO empty will be set when the last element is placed from the FIFO to the transmit buffer
- send will start with the next SCLK cycle
When doing manual control, the timing depends on how fast you SCLK is.
I just found out about the SPI_SpiBusIsBusy() function, that gives you the status of the SS# line. When you use that you get the exact information when transmission has ended, and SS# got negated. Then you can change D/C#.
But I agree that a diagram as in the UDB-based SPI component would be very helpful. Maybe request one by filing a support case...