From the Architecture TRM -
I was able to route into Ports 0 - 3.
Thanks for the reply!
Before I start, I fully admit I am an idiot, and probably am missing something obvious.
The PSoC creator document that mentions Transparent mode indicates that mode is only for digital. (http://www.cypress.com/modules/training/PSoCCreator112/Attachments/PSoC%20Creator%20112%20-%20Intro%20to%20API%20Generation.pdf)
I see you can use P4 pins for capSense, but I haven't investigated that magic twist yet. It probably requires the capsense block, and the user has no control over which pins it uses. Similar to PSoC 4 uart i/o pins.
Back to my original question, what pins should I put the iDAC on, if that is even a possibility? I'm beginning to suspect that the iDAC is *not* available for general purpose use on the PSoC 4. If so, that is fine, I can go to another processor and stop working with this one.
So, nothing so far works that I have tried. The datasheet is not giving me a clue. Pins from port 2 for SAR don't word, pins from port 4 for iDAC don't work. I find no documentation that indicates where iDAC is brought out for PSoC 4, except for the crossbar switch map in PSoC creator, which is obviously wrong.
So, is the result that the iDAC's can only be used with CapSense?
This might be of some help -
http://www.cypress.com/?rID=93401 AN86439 - PSoC® 4 - Using GPIO Pins
What you are seeing is a part with substantial reduction in flexibility/capability = low cost.
So the PSOC 4 does not have all the flexible routing capability as the 3/5LP parts.
Documentation is a challenge, I think when all is said and done Cypress will exceed
10,000 pages of docs for the 5LP. The more we ask for in parts, the greater challenge
for the documentors, which are largely the design engineers we want to spend time on
new capabilities. Major conundrum for the industry at large.
I did route just an IDAC into random pin in each of ports 0 - 3. Did not test however.
If you read TRM sections, in addition to datasheets and ap notes, there is in general
more information there.
In short there will be continuing challenges on docs as the design EEs are doing the docs
and as we all know EEs are not generally thought to be English majors, so docs reflect that.
At least in my case, English my native language, and my grades in those classes bordered on
Please, can you post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
First, I want to say, "I am an idiot!" I looked back at my original post and I *never* asked the question of where to put the iDAC output! Obviously, I don't understand the english language either. Please excuse me while I open my mouth to exchange feet.
I apologize for impuning that my question wasn't being answered. It was never asked! I'm sorry, and that is why I like to preface some of my posts with "I'm an idiot," because I usually make those kinds of idiot mistakes. mea culpa! (my fault)
I was able to get the iDAC routed during our ice storm(s) this weekend working from home. It turned out that P3 works. I found out that it would when I stumbled across an iDAC excample for PSoC 4 in PSoC creator example. I *thought* I looked there previously, but obviously I can't read very well.
Also, I should have allowed PSoC Creator to automagically assign the pin number. That would have given me my first clue as to what to do.
One interesting thing, once I got a *correct* pin for the iDAC output, the SAR input magically unbroke itself and routed. One of my surprises was when the iDAC did not route, the SAR input showed an error also.
In terms of documentation, Cypress documentation is up there with the best I've seen in the industry. As an engineer, I often overlook the fact that false emotions can be read into written facts, especially when incorrectly phrased. I'll keep working on that problem of mine. I did not mean to imply the documentation was bad, just missing an odd fact here or there.
In terms of responsiveness, Cypress tech support is *way* above any of the other companies. Head and shoulders. If Cypress were to come out with FPGA's of decent size, based on the CMOS technology of your PSoC5LP, I would be an early adopter.