3 Replies Latest reply on Mar 2, 2015 6:12 AM by user_246598725

    Is there an easy way to select from multiple external RAM chips with EMIF

    seth.henry

      I was enthusiastic when I saw that the PSoC5 LP parts have working EMIF controllers, as I really like the flexibility that the PSoC parts provide compared to normal microcontrollers. I have a project right now that I would like to use a PSoC5 LP on, but I need to attach multiple memories to it - specifically a 8Mbit (512kx16) async SRAM and an FPGA with an async SRAM-like interface. It would be nice if these were memory mapped together such that a DMA could be set up to copy data from the FPGA to the SRAM and vice-versa.

         

      The trouble is that there doesn't appear to be a way to use the address lines to selectively enable the parts. Ordinarily, I would just drop a bit of logic on a the high address line to control which part gets the CEn signal, and I can do it here, but it seems like there should be some way to do this internally. Other than routing the MSB of the address bus back in on another pin, is there a way to do this?

         

      Thanks!

        • 1. Re: Is there an easy way to select from multiple external RAM chips with EMIF
          gautam.das.g

          Hi jshamlet,

             

           

             

          The EMIF Block in PSoC 5LP can support interface with upto 16MB of SRAM. It can be configured to support upto 24 address lines and 16 data lines.

             

          The external memory interface is memory mapped to the space 0x60000000 to 0x61FFFFFF.

             

          One way which I can think of to interface two 8MB memories (SRAM and FPGA) would be to configure the EMIF to 24-bit address. The MSB (24th Bit) of the address will decide which memory is being selected.

             

          Consider the schematic below:

             

           

             

           

             

           

             

           

             

          1) In the above schematic, a digital input pin is to be used which is externally connected to the 24th Address bit.

             

          2) This pin acts as a select line for the de-multiplexer which routes the Chip Enable signal to the approprioate memory device (SRAM or FPGA).

             

          3) When the 24th Address line is 0, the lower 8MB address is being accessed,  when it is high the higher 8MB address is being accessed.

             

           

             

          Let us know if this helps.

             

           

             

           

             

          Thanks,

             

          Gautam Das

          • 2. Re: Is there an easy way to select from multiple external RAM chips with EMIF
            seth.henry

            I'm sorry, but I wasn't specific enough. I actually have implemented something very similar to what you have drawn, only I used a LUT. Your solution is equivalent, but a bit easier to follow.

               

            The real question was whether there was a way to access the MSB of the address bus directly without dragging it in through a pin. IOW, can you attach a UDB to the EMIF controller internally. As it stands, I am "wasting" an additional I/O pin in addition to the 4 unused address lines.

            • 3. Re: Is there an easy way to select from multiple external RAM chips with EMIF
              user_246598725

              The real question was whether there was a way to access the MSB of the address bus directly without dragging it in through a pin. IOW, can you attach a UDB to the EMIF controller internally. As it stands, I am "wasting" an additional I/O pin in addition to the 4 unused address lines.

                 

              I've had a similar issue and opened a seperate posting about it:

                 

              http://www.cypress.com/?app=forum&id=2233&rID=106782

                 

               

                 

              Regards,

                 

               

                 

              Ralf